summaryrefslogtreecommitdiff
path: root/src/gallium/drivers/radeonsi/si_state_shaders.c
blob: 941a397525e2daca680523f5202f10c0a24aa1a8 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751
3752
3753
3754
3755
3756
3757
3758
3759
3760
3761
3762
3763
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811
3812
3813
3814
3815
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973
3974
3975
3976
3977
3978
3979
3980
3981
3982
3983
3984
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001
4002
4003
4004
4005
4006
4007
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051
4052
4053
4054
4055
4056
4057
4058
4059
4060
4061
4062
4063
4064
4065
4066
4067
4068
4069
4070
4071
4072
4073
4074
4075
4076
4077
4078
4079
4080
4081
4082
4083
4084
4085
4086
4087
4088
4089
4090
4091
4092
4093
4094
4095
4096
4097
4098
4099
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
4110
4111
4112
4113
4114
4115
4116
4117
4118
4119
4120
4121
4122
4123
4124
4125
4126
4127
4128
4129
4130
4131
4132
4133
4134
4135
4136
4137
4138
4139
4140
4141
4142
4143
4144
4145
4146
4147
4148
4149
4150
4151
4152
4153
4154
4155
4156
4157
4158
4159
4160
4161
4162
4163
4164
4165
4166
4167
4168
4169
4170
/*
 * Copyright 2012 Advanced Micro Devices, Inc.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * on the rights to use, copy, modify, merge, publish, distribute, sub
 * license, and/or sell copies of the Software, and to permit persons to whom
 * the Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#include "si_build_pm4.h"
#include "sid.h"

#include "compiler/nir/nir_serialize.h"
#include "nir/tgsi_to_nir.h"
#include "tgsi/tgsi_parse.h"
#include "util/hash_table.h"
#include "util/crc32.h"
#include "util/u_async_debug.h"
#include "util/u_memory.h"
#include "util/u_prim.h"

#include "util/disk_cache.h"
#include "util/mesa-sha1.h"
#include "ac_exp_param.h"
#include "ac_shader_util.h"

/* SHADER_CACHE */

/**
 * Return the IR key for the shader cache.
 */
void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es,
			 unsigned char ir_sha1_cache_key[20])
{
	struct blob blob = {};
	unsigned ir_size;
	void *ir_binary;

	if (sel->tokens) {
		ir_binary = sel->tokens;
		ir_size = tgsi_num_tokens(sel->tokens) *
			  sizeof(struct tgsi_token);
	} else if (sel->nir_binary) {
		ir_binary = sel->nir_binary;
		ir_size = sel->nir_size;
	} else {
		assert(sel->nir);

		blob_init(&blob);
		nir_serialize(&blob, sel->nir, true);
		ir_binary = blob.data;
		ir_size = blob.size;
	}

	/* These settings affect the compilation, but they are not derived
	 * from the input shader IR.
	 */
	unsigned shader_variant_flags = 0;

	if (ngg)
		shader_variant_flags |= 1 << 0;
	if (sel->nir)
		shader_variant_flags |= 1 << 1;
	if (si_get_wave_size(sel->screen, sel->type, ngg, es) == 32)
		shader_variant_flags |= 1 << 2;
	if (sel->force_correct_derivs_after_kill)
		shader_variant_flags |= 1 << 3;

	struct mesa_sha1 ctx;
	_mesa_sha1_init(&ctx);
	_mesa_sha1_update(&ctx, &shader_variant_flags, 4);
	_mesa_sha1_update(&ctx, ir_binary, ir_size);
	if (sel->type == PIPE_SHADER_VERTEX ||
	    sel->type == PIPE_SHADER_TESS_EVAL ||
	    sel->type == PIPE_SHADER_GEOMETRY)
		_mesa_sha1_update(&ctx, &sel->so, sizeof(sel->so));
	_mesa_sha1_final(&ctx, ir_sha1_cache_key);

	if (ir_binary == blob.data)
		blob_finish(&blob);
}

/** Copy "data" to "ptr" and return the next dword following copied data. */
static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
{
	/* data may be NULL if size == 0 */
	if (size)
		memcpy(ptr, data, size);
	ptr += DIV_ROUND_UP(size, 4);
	return ptr;
}

/** Read data from "ptr". Return the next dword following the data. */
static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
{
	memcpy(data, ptr, size);
	ptr += DIV_ROUND_UP(size, 4);
	return ptr;
}

/**
 * Write the size as uint followed by the data. Return the next dword
 * following the copied data.
 */
static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
{
	*ptr++ = size;
	return write_data(ptr, data, size);
}

/**
 * Read the size as uint followed by the data. Return both via parameters.
 * Return the next dword following the data.
 */
static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
{
	*size = *ptr++;
	assert(*data == NULL);
	if (!*size)
		return ptr;
	*data = malloc(*size);
	return read_data(ptr, *data, *size);
}

/**
 * Return the shader binary in a buffer. The first 4 bytes contain its size
 * as integer.
 */
static void *si_get_shader_binary(struct si_shader *shader)
{
	/* There is always a size of data followed by the data itself. */
	unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
				strlen(shader->binary.llvm_ir_string) + 1 : 0;

	/* Refuse to allocate overly large buffers and guard against integer
	 * overflow. */
	if (shader->binary.elf_size > UINT_MAX / 4 ||
	    llvm_ir_size > UINT_MAX / 4)
		return NULL;

	unsigned size =
		4 + /* total size */
		4 + /* CRC32 of the data below */
		align(sizeof(shader->config), 4) +
		align(sizeof(shader->info), 4) +
		4 + align(shader->binary.elf_size, 4) +
		4 + align(llvm_ir_size, 4);
	void *buffer = CALLOC(1, size);
	uint32_t *ptr = (uint32_t*)buffer;

	if (!buffer)
		return NULL;

	*ptr++ = size;
	ptr++; /* CRC32 is calculated at the end. */

	ptr = write_data(ptr, &shader->config, sizeof(shader->config));
	ptr = write_data(ptr, &shader->info, sizeof(shader->info));
	ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
	ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
	assert((char *)ptr - (char *)buffer == size);

	/* Compute CRC32. */
	ptr = (uint32_t*)buffer;
	ptr++;
	*ptr = util_hash_crc32(ptr + 1, size - 8);

	return buffer;
}

static bool si_load_shader_binary(struct si_shader *shader, void *binary)
{
	uint32_t *ptr = (uint32_t*)binary;
	uint32_t size = *ptr++;
	uint32_t crc32 = *ptr++;
	unsigned chunk_size;
	unsigned elf_size;

	if (util_hash_crc32(ptr, size - 8) != crc32) {
		fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
		return false;
	}

	ptr = read_data(ptr, &shader->config, sizeof(shader->config));
	ptr = read_data(ptr, &shader->info, sizeof(shader->info));
	ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
			 &elf_size);
	shader->binary.elf_size = elf_size;
	ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);

	return true;
}

/**
 * Insert a shader into the cache. It's assumed the shader is not in the cache.
 * Use si_shader_cache_load_shader before calling this.
 */
void si_shader_cache_insert_shader(struct si_screen *sscreen,
				   unsigned char ir_sha1_cache_key[20],
				   struct si_shader *shader,
				   bool insert_into_disk_cache)
{
	void *hw_binary;
	struct hash_entry *entry;
	uint8_t key[CACHE_KEY_SIZE];

	entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
	if (entry)
		return; /* already added */

	hw_binary = si_get_shader_binary(shader);
	if (!hw_binary)
		return;

	if (_mesa_hash_table_insert(sscreen->shader_cache,
				    mem_dup(ir_sha1_cache_key, 20),
				    hw_binary) == NULL) {
		FREE(hw_binary);
		return;
	}

	if (sscreen->disk_shader_cache && insert_into_disk_cache) {
		disk_cache_compute_key(sscreen->disk_shader_cache,
				       ir_sha1_cache_key, 20, key);
		disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
			       *((uint32_t *) hw_binary), NULL);
	}
}

bool si_shader_cache_load_shader(struct si_screen *sscreen,
				 unsigned char ir_sha1_cache_key[20],
				 struct si_shader *shader)
{
	struct hash_entry *entry =
		_mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
	if (!entry) {
		if (sscreen->disk_shader_cache) {
			unsigned char sha1[CACHE_KEY_SIZE];

			disk_cache_compute_key(sscreen->disk_shader_cache,
					       ir_sha1_cache_key, 20, sha1);

			size_t binary_size;
			uint8_t *buffer =
				disk_cache_get(sscreen->disk_shader_cache,
					       sha1, &binary_size);
			if (!buffer)
				return false;

			if (binary_size < sizeof(uint32_t) ||
			    *((uint32_t*)buffer) != binary_size) {
				 /* Something has gone wrong discard the item
				  * from the cache and rebuild/link from
				  * source.
				  */
				assert(!"Invalid radeonsi shader disk cache "
				       "item!");

				disk_cache_remove(sscreen->disk_shader_cache,
						  sha1);
				free(buffer);

				return false;
			}

			if (!si_load_shader_binary(shader, buffer)) {
				free(buffer);
				return false;
			}
			free(buffer);

			si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key,
						      shader, false);
		} else {
			return false;
		}
	} else {
		if (!si_load_shader_binary(shader, entry->data))
			return false;
	}
	p_atomic_inc(&sscreen->num_shader_cache_hits);
	return true;
}

static uint32_t si_shader_cache_key_hash(const void *key)
{
	/* Take the first dword of SHA1. */
	return *(uint32_t*)key;
}

static bool si_shader_cache_key_equals(const void *a, const void *b)
{
	/* Compare SHA1s. */
	return memcmp(a, b, 20) == 0;
}

static void si_destroy_shader_cache_entry(struct hash_entry *entry)
{
	FREE((void*)entry->key);
	FREE(entry->data);
}

bool si_init_shader_cache(struct si_screen *sscreen)
{
	(void) simple_mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
	sscreen->shader_cache =
		_mesa_hash_table_create(NULL,
					si_shader_cache_key_hash,
					si_shader_cache_key_equals);

	return sscreen->shader_cache != NULL;
}

void si_destroy_shader_cache(struct si_screen *sscreen)
{
	if (sscreen->shader_cache)
		_mesa_hash_table_destroy(sscreen->shader_cache,
					 si_destroy_shader_cache_entry);
	simple_mtx_destroy(&sscreen->shader_cache_mutex);
}

/* SHADER STATES */

static void si_set_tesseval_regs(struct si_screen *sscreen,
				 const struct si_shader_selector *tes,
				 struct si_pm4_state *pm4)
{
	const struct tgsi_shader_info *info = &tes->info;
	unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
	unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
	bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
	bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
	unsigned type, partitioning, topology, distribution_mode;

	switch (tes_prim_mode) {
	case PIPE_PRIM_LINES:
		type = V_028B6C_TESS_ISOLINE;
		break;
	case PIPE_PRIM_TRIANGLES:
		type = V_028B6C_TESS_TRIANGLE;
		break;
	case PIPE_PRIM_QUADS:
		type = V_028B6C_TESS_QUAD;
		break;
	default:
		assert(0);
		return;
	}

	switch (tes_spacing) {
	case PIPE_TESS_SPACING_FRACTIONAL_ODD:
		partitioning = V_028B6C_PART_FRAC_ODD;
		break;
	case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
		partitioning = V_028B6C_PART_FRAC_EVEN;
		break;
	case PIPE_TESS_SPACING_EQUAL:
		partitioning = V_028B6C_PART_INTEGER;
		break;
	default:
		assert(0);
		return;
	}

	if (tes_point_mode)
		topology = V_028B6C_OUTPUT_POINT;
	else if (tes_prim_mode == PIPE_PRIM_LINES)
		topology = V_028B6C_OUTPUT_LINE;
	else if (tes_vertex_order_cw)
		/* for some reason, this must be the other way around */
		topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
	else
		topology = V_028B6C_OUTPUT_TRIANGLE_CW;

	if (sscreen->info.has_distributed_tess) {
		if (sscreen->info.family == CHIP_FIJI ||
		    sscreen->info.family >= CHIP_POLARIS10)
			distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
		else
			distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
	} else
		distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;

	assert(pm4->shader);
	pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
				    S_028B6C_PARTITIONING(partitioning) |
				    S_028B6C_TOPOLOGY(topology) |
				    S_028B6C_DISTRIBUTION_MODE(distribution_mode);
}

/* Polaris needs different VTX_REUSE_DEPTH settings depending on
 * whether the "fractional odd" tessellation spacing is used.
 *
 * Possible VGT configurations and which state should set the register:
 *
 *   Reg set in | VGT shader configuration   | Value
 * ------------------------------------------------------
 *     VS as VS | VS                         | 30
 *     VS as ES | ES -> GS -> VS             | 30
 *    TES as VS | LS -> HS -> VS             | 14 or 30
 *    TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
 *
 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
 */
static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
					 struct si_shader_selector *sel,
					 struct si_shader *shader,
					 struct si_pm4_state *pm4)
{
	unsigned type = sel->type;

	if (sscreen->info.family < CHIP_POLARIS10 ||
	    sscreen->info.chip_class >= GFX10)
		return;

	/* VS as VS, or VS as ES: */
	if ((type == PIPE_SHADER_VERTEX &&
	     (!shader ||
	      (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
	    /* TES as VS, or TES as ES: */
	    type == PIPE_SHADER_TESS_EVAL) {
		unsigned vtx_reuse_depth = 30;

		if (type == PIPE_SHADER_TESS_EVAL &&
		    sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
		    PIPE_TESS_SPACING_FRACTIONAL_ODD)
			vtx_reuse_depth = 14;

		assert(pm4->shader);
		pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
	}
}

static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
{
	if (shader->pm4)
		si_pm4_clear_state(shader->pm4);
	else
		shader->pm4 = CALLOC_STRUCT(si_pm4_state);

	if (shader->pm4) {
		shader->pm4->shader = shader;
		return shader->pm4;
	} else {
		fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
		return NULL;
	}
}

static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
{
	/* Add the pointer to VBO descriptors. */
	return num_always_on_user_sgprs + 1;
}

/* Return VGPR_COMP_CNT for the API vertex shader. This can be hw LS, LSHS, ES, ESGS, VS. */
static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen *sscreen,
					struct si_shader *shader, bool legacy_vs_prim_id)
{
	assert(shader->selector->type == PIPE_SHADER_VERTEX ||
	       (shader->previous_stage_sel &&
		shader->previous_stage_sel->type == PIPE_SHADER_VERTEX));

	/* GFX6-9 LS    (VertexID, RelAutoindex,                InstanceID / StepRate0(==1), ...).
	 * GFX6-9 ES,VS (VertexID, InstanceID / StepRate0(==1), VSPrimID,                    ...)
	 * GFX10  LS    (VertexID, RelAutoindex,                UserVGPR1,                   InstanceID).
	 * GFX10  ES,VS (VertexID, UserVGPR0,                   UserVGPR1 or VSPrimID,       UserVGPR2 or InstanceID)
	 */
	bool is_ls = shader->selector->type == PIPE_SHADER_TESS_CTRL || shader->key.as_ls;

	if (sscreen->info.chip_class >= GFX10 && shader->info.uses_instanceid)
		return 3;
	else if ((is_ls && shader->info.uses_instanceid) || legacy_vs_prim_id)
		return 2;
	else if (is_ls || shader->info.uses_instanceid)
		return 1;
	else
		return 0;
}

static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
{
	struct si_pm4_state *pm4;
	uint64_t va;

	assert(sscreen->info.chip_class <= GFX8);

	pm4 = si_get_shader_pm4_state(shader);
	if (!pm4)
		return;

	va = shader->bo->gpu_address;
	si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);

	si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
	si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));

	shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
			   S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
		           S_00B528_VGPR_COMP_CNT(si_get_vs_vgpr_comp_cnt(sscreen, shader, false)) |
			   S_00B528_DX10_CLAMP(1) |
			   S_00B528_FLOAT_MODE(shader->config.float_mode);
	shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
			   S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
}

static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
{
	struct si_pm4_state *pm4;
	uint64_t va;

	pm4 = si_get_shader_pm4_state(shader);
	if (!pm4)
		return;

	va = shader->bo->gpu_address;
	si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);

	if (sscreen->info.chip_class >= GFX9) {
		if (sscreen->info.chip_class >= GFX10) {
			si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
			si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
		} else {
			si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
			si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
		}

		unsigned num_user_sgprs =
			si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);

		shader->config.rsrc2 =
			S_00B42C_USER_SGPR(num_user_sgprs) |
			S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);

		if (sscreen->info.chip_class >= GFX10)
			shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
		else
			shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
	} else {
		si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
		si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));

		shader->config.rsrc2 =
			S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
			S_00B42C_OC_LDS_EN(1) |
			S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
	}

	si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
		       S_00B428_VGPRS((shader->config.num_vgprs - 1) /
				      (sscreen->ge_wave_size == 32 ? 8 : 4)) |
		       (sscreen->info.chip_class <= GFX9 ?
				S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
		       S_00B428_DX10_CLAMP(1) |
		       S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
		       S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
		       S_00B428_FLOAT_MODE(shader->config.float_mode) |
		       S_00B428_LS_VGPR_COMP_CNT(sscreen->info.chip_class >= GFX9 ?
						 si_get_vs_vgpr_comp_cnt(sscreen, shader, false) : 0));

	if (sscreen->info.chip_class <= GFX8) {
		si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
			       shader->config.rsrc2);
	}
}

static void si_emit_shader_es(struct si_context *sctx)
{
	struct si_shader *shader = sctx->queued.named.es->shader;
	unsigned initial_cdw = sctx->gfx_cs->current.cdw;

	if (!shader)
		return;

	radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
				   SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
				   shader->selector->esgs_itemsize / 4);

	if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
		radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
					   SI_TRACKED_VGT_TF_PARAM,
					   shader->vgt_tf_param);

	if (shader->vgt_vertex_reuse_block_cntl)
		radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
					   SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
					   shader->vgt_vertex_reuse_block_cntl);

	if (initial_cdw != sctx->gfx_cs->current.cdw)
		sctx->context_roll = true;
}

static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
{
	struct si_pm4_state *pm4;
	unsigned num_user_sgprs;
	unsigned vgpr_comp_cnt;
	uint64_t va;
	unsigned oc_lds_en;

	assert(sscreen->info.chip_class <= GFX8);

	pm4 = si_get_shader_pm4_state(shader);
	if (!pm4)
		return;

	pm4->atom.emit = si_emit_shader_es;
	va = shader->bo->gpu_address;
	si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);

	if (shader->selector->type == PIPE_SHADER_VERTEX) {
		vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
		num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
	} else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
		vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
		num_user_sgprs = SI_TES_NUM_USER_SGPR;
	} else
		unreachable("invalid shader selector type");

	oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;

	si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
	si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
	si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
		       S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
		       S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
		       S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
		       S_00B328_DX10_CLAMP(1) |
		       S_00B328_FLOAT_MODE(shader->config.float_mode));
	si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
		       S_00B32C_USER_SGPR(num_user_sgprs) |
		       S_00B32C_OC_LDS_EN(oc_lds_en) |
		       S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));

	if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
		si_set_tesseval_regs(sscreen, shader->selector, pm4);

	polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
}

void gfx9_get_gs_info(struct si_shader_selector *es,
		      struct si_shader_selector *gs,
		      struct gfx9_gs_info *out)
{
	unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
	unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
	bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
			      input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;

	/* All these are in dwords: */
	/* We can't allow using the whole LDS, because GS waves compete with
	 * other shader stages for LDS space. */
	const unsigned max_lds_size = 8 * 1024;
	const unsigned esgs_itemsize = es->esgs_itemsize / 4;
	unsigned esgs_lds_size;

	/* All these are per subgroup: */
	const unsigned max_out_prims = 32 * 1024;
	const unsigned max_es_verts = 255;
	const unsigned ideal_gs_prims = 64;
	unsigned max_gs_prims, gs_prims;
	unsigned min_es_verts, es_verts, worst_case_es_verts;

	if (uses_adjacency || gs_num_invocations > 1)
		max_gs_prims = 127 / gs_num_invocations;
	else
		max_gs_prims = 255;

	/* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
	 * Make sure we don't go over the maximum value.
	 */
	if (gs->gs_max_out_vertices > 0) {
		max_gs_prims = MIN2(max_gs_prims,
				    max_out_prims /
				    (gs->gs_max_out_vertices * gs_num_invocations));
	}
	assert(max_gs_prims > 0);

	/* If the primitive has adjacency, halve the number of vertices
	 * that will be reused in multiple primitives.
	 */
	min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);

	gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
	worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);

	/* Compute ESGS LDS size based on the worst case number of ES vertices
	 * needed to create the target number of GS prims per subgroup.
	 */
	esgs_lds_size = esgs_itemsize * worst_case_es_verts;

	/* If total LDS usage is too big, refactor partitions based on ratio
	 * of ESGS item sizes.
	 */
	if (esgs_lds_size > max_lds_size) {
		/* Our target GS Prims Per Subgroup was too large. Calculate
		 * the maximum number of GS Prims Per Subgroup that will fit
		 * into LDS, capped by the maximum that the hardware can support.
		 */
		gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
				max_gs_prims);
		assert(gs_prims > 0);
		worst_case_es_verts = MIN2(min_es_verts * gs_prims,
					   max_es_verts);

		esgs_lds_size = esgs_itemsize * worst_case_es_verts;
		assert(esgs_lds_size <= max_lds_size);
	}

	/* Now calculate remaining ESGS information. */
	if (esgs_lds_size)
		es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
	else
		es_verts = max_es_verts;

	/* Vertices for adjacency primitives are not always reused, so restore
	 * it for ES_VERTS_PER_SUBGRP.
	 */
	min_es_verts = gs->gs_input_verts_per_prim;

	/* For normal primitives, the VGT only checks if they are past the ES
	 * verts per subgroup after allocating a full GS primitive and if they
	 * are, kick off a new subgroup.  But if those additional ES verts are
	 * unique (e.g. not reused) we need to make sure there is enough LDS
	 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
	 */
	es_verts -= min_es_verts - 1;

	out->es_verts_per_subgroup = es_verts;
	out->gs_prims_per_subgroup = gs_prims;
	out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
	out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
				      gs->gs_max_out_vertices;
	out->esgs_ring_size = 4 * esgs_lds_size;

	assert(out->max_prims_per_subgroup <= max_out_prims);
}

static void si_emit_shader_gs(struct si_context *sctx)
{
	struct si_shader *shader = sctx->queued.named.gs->shader;
	unsigned initial_cdw = sctx->gfx_cs->current.cdw;

	if (!shader)
		return;

	/* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
	 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
	radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
				    SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
				    shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
				    shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
				    shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);

	/* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
	radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
				   SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
				   shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);

	/* R_028B38_VGT_GS_MAX_VERT_OUT */
	radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
				   SI_TRACKED_VGT_GS_MAX_VERT_OUT,
				   shader->ctx_reg.gs.vgt_gs_max_vert_out);

	/* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
	 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
	radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
				    SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
				    shader->ctx_reg.gs.vgt_gs_vert_itemsize,
				    shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
				    shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
				    shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);

	/* R_028B90_VGT_GS_INSTANCE_CNT */
	radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
				   SI_TRACKED_VGT_GS_INSTANCE_CNT,
				   shader->ctx_reg.gs.vgt_gs_instance_cnt);

	if (sctx->chip_class >= GFX9) {
		/* R_028A44_VGT_GS_ONCHIP_CNTL */
		radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
					   SI_TRACKED_VGT_GS_ONCHIP_CNTL,
					   shader->ctx_reg.gs.vgt_gs_onchip_cntl);
		/* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
		radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
					   SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
					   shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
		/* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
		radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
					   SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
					   shader->ctx_reg.gs.vgt_esgs_ring_itemsize);

		if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
			radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
						   SI_TRACKED_VGT_TF_PARAM,
						   shader->vgt_tf_param);
		if (shader->vgt_vertex_reuse_block_cntl)
			radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
						   SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
						   shader->vgt_vertex_reuse_block_cntl);
	}

	if (initial_cdw != sctx->gfx_cs->current.cdw)
		sctx->context_roll = true;
}

static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
{
	struct si_shader_selector *sel = shader->selector;
	const ubyte *num_components = sel->info.num_stream_output_components;
	unsigned gs_num_invocations = sel->gs_num_invocations;
	struct si_pm4_state *pm4;
	uint64_t va;
	unsigned max_stream = sel->max_gs_stream;
	unsigned offset;

	pm4 = si_get_shader_pm4_state(shader);
	if (!pm4)
		return;

	pm4->atom.emit = si_emit_shader_gs;

	offset = num_components[0] * sel->gs_max_out_vertices;
	shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;

	if (max_stream >= 1)
		offset += num_components[1] * sel->gs_max_out_vertices;
	shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;

	if (max_stream >= 2)
		offset += num_components[2] * sel->gs_max_out_vertices;
	shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;

	if (max_stream >= 3)
		offset += num_components[3] * sel->gs_max_out_vertices;
	shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;

	/* The GSVS_RING_ITEMSIZE register takes 15 bits */
	assert(offset < (1 << 15));

	shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;

	shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
	shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
	shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
	shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;

	shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
						 S_028B90_ENABLE(gs_num_invocations > 0);

	va = shader->bo->gpu_address;
	si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);

	if (sscreen->info.chip_class >= GFX9) {
		unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
		unsigned es_type = shader->key.part.gs.es->type;
		unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;

		if (es_type == PIPE_SHADER_VERTEX) {
			es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
		} else if (es_type == PIPE_SHADER_TESS_EVAL)
			es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
		else
			unreachable("invalid shader selector type");

		/* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
		 * VGPR[0:4] are always loaded.
		 */
		if (sel->info.uses_invocationid)
			gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
		else if (sel->info.uses_primid)
			gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
		else if (input_prim >= PIPE_PRIM_TRIANGLES)
			gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
		else
			gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */

		unsigned num_user_sgprs;
		if (es_type == PIPE_SHADER_VERTEX)
			num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
		else
			num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;

		if (sscreen->info.chip_class >= GFX10) {
			si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
			si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
		} else {
			si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
			si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
		}

		uint32_t rsrc1 =
			S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
			S_00B228_DX10_CLAMP(1) |
			S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
			S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
			S_00B228_FLOAT_MODE(shader->config.float_mode) |
			S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
		uint32_t rsrc2 =
			S_00B22C_USER_SGPR(num_user_sgprs) |
			S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
			S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
			S_00B22C_LDS_SIZE(shader->config.lds_size) |
			S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);

		if (sscreen->info.chip_class >= GFX10) {
			rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
		} else {
			rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
			rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
		}

		si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
		si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);

		shader->ctx_reg.gs.vgt_gs_onchip_cntl =
			S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
			S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
			S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
		shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
			S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
		shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
			shader->key.part.gs.es->esgs_itemsize / 4;

		if (es_type == PIPE_SHADER_TESS_EVAL)
			si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);

		polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
					     NULL, pm4);
	} else {
		si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
		si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));

		si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
			       S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
			       S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
			       S_00B228_DX10_CLAMP(1) |
			       S_00B228_FLOAT_MODE(shader->config.float_mode));
		si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
			       S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
			       S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
	}
}

/* Common tail code for NGG primitive shaders. */
static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
				       struct si_shader *shader,
				       unsigned initial_cdw)
{
	radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
				   SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
				   shader->ctx_reg.ngg.ge_max_output_per_subgroup);
	radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
				   SI_TRACKED_GE_NGG_SUBGRP_CNTL,
				   shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
	radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
				   SI_TRACKED_VGT_PRIMITIVEID_EN,
				   shader->ctx_reg.ngg.vgt_primitiveid_en);
	radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
				   SI_TRACKED_VGT_GS_ONCHIP_CNTL,
				   shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
	radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
				   SI_TRACKED_VGT_GS_INSTANCE_CNT,
				   shader->ctx_reg.ngg.vgt_gs_instance_cnt);
	radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
				   SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
				   shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
	radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
				   SI_TRACKED_SPI_VS_OUT_CONFIG,
				   shader->ctx_reg.ngg.spi_vs_out_config);
	radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
				   SI_TRACKED_SPI_SHADER_IDX_FORMAT,
				   shader->ctx_reg.ngg.spi_shader_idx_format,
				   shader->ctx_reg.ngg.spi_shader_pos_format);
	radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
				   SI_TRACKED_PA_CL_VTE_CNTL,
				   shader->ctx_reg.ngg.pa_cl_vte_cntl);
	radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL,
				   SI_TRACKED_PA_CL_NGG_CNTL,
				   shader->ctx_reg.ngg.pa_cl_ngg_cntl);

	radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
				       SI_TRACKED_PA_CL_VS_OUT_CNTL__VS,
				       shader->pa_cl_vs_out_cntl,
				       SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);

	if (initial_cdw != sctx->gfx_cs->current.cdw)
		sctx->context_roll = true;
}

static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
{
	struct si_shader *shader = sctx->queued.named.gs->shader;
	unsigned initial_cdw = sctx->gfx_cs->current.cdw;

	if (!shader)
		return;

	gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
}

static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
{
	struct si_shader *shader = sctx->queued.named.gs->shader;
	unsigned initial_cdw = sctx->gfx_cs->current.cdw;

	if (!shader)
		return;

	radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
				   SI_TRACKED_VGT_TF_PARAM,
				   shader->vgt_tf_param);

	gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
}

static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
{
	struct si_shader *shader = sctx->queued.named.gs->shader;
	unsigned initial_cdw = sctx->gfx_cs->current.cdw;

	if (!shader)
		return;

	radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
				   SI_TRACKED_VGT_GS_MAX_VERT_OUT,
				   shader->ctx_reg.ngg.vgt_gs_max_vert_out);

	gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
}

static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
{
	struct si_shader *shader = sctx->queued.named.gs->shader;
	unsigned initial_cdw = sctx->gfx_cs->current.cdw;

	if (!shader)
		return;

	radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
				   SI_TRACKED_VGT_GS_MAX_VERT_OUT,
				   shader->ctx_reg.ngg.vgt_gs_max_vert_out);
	radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
				   SI_TRACKED_VGT_TF_PARAM,
				   shader->vgt_tf_param);

	gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
}

unsigned si_get_input_prim(const struct si_shader_selector *gs)
{
	if (gs->type == PIPE_SHADER_GEOMETRY)
		return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];

	if (gs->type == PIPE_SHADER_TESS_EVAL) {
		if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
			return PIPE_PRIM_POINTS;
		if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
			return PIPE_PRIM_LINES;
		return PIPE_PRIM_TRIANGLES;
	}

	/* TODO: Set this correctly if the primitive type is set in the shader key. */
	return PIPE_PRIM_TRIANGLES; /* worst case for all callers */
}

static unsigned si_get_vs_out_cntl(const struct si_shader_selector *sel, bool ngg)
{
	bool misc_vec_ena =
		sel->info.writes_psize || (sel->info.writes_edgeflag && !ngg) ||
		sel->info.writes_layer || sel->info.writes_viewport_index;
	return S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
	       S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag && !ngg) |
	       S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
	       S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
	       S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
	       S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
}

/**
 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
 * in NGG mode.
 */
static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
{
	const struct si_shader_selector *gs_sel = shader->selector;
	const struct tgsi_shader_info *gs_info = &gs_sel->info;
	enum pipe_shader_type gs_type = shader->selector->type;
	const struct si_shader_selector *es_sel =
		shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
	const struct tgsi_shader_info *es_info = &es_sel->info;
	enum pipe_shader_type es_type = es_sel->type;
	unsigned num_user_sgprs;
	unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
	uint64_t va;
	unsigned window_space =
		gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
	bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
	unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
	unsigned input_prim = si_get_input_prim(gs_sel);
	bool break_wave_at_eoi = false;
	struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
	if (!pm4)
		return;

	if (es_type == PIPE_SHADER_TESS_EVAL) {
		pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
								 : gfx10_emit_shader_ngg_tess_nogs;
	} else {
		pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
								 : gfx10_emit_shader_ngg_notess_nogs;
	}

	va = shader->bo->gpu_address;
	si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);

	if (es_type == PIPE_SHADER_VERTEX) {
		es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);

		if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
			num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
					 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
		} else {
			num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
		}
	} else {
		assert(es_type == PIPE_SHADER_TESS_EVAL);
		es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
		num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;

		if (es_enable_prim_id || gs_info->uses_primid)
			break_wave_at_eoi = true;
	}

	/* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
	 * VGPR[0:4] are always loaded.
	 *
	 * Vertex shaders always need to load VGPR3, because they need to
	 * pass edge flags for decomposed primitives (such as quads) to the PA
	 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
	 */
	if (gs_info->uses_invocationid || gs_type == PIPE_SHADER_VERTEX)
		gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
	else if (gs_info->uses_primid)
		gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
	else if (input_prim >= PIPE_PRIM_TRIANGLES)
		gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
	else
		gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */

	si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
	si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
	si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
		       S_00B228_VGPRS((shader->config.num_vgprs - 1) /
				      (sscreen->ge_wave_size == 32 ? 8 : 4)) |
		       S_00B228_FLOAT_MODE(shader->config.float_mode) |
		       S_00B228_DX10_CLAMP(1) |
		       S_00B228_MEM_ORDERED(1) |
		       S_00B228_WGP_MODE(1) |
		       S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
	si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
		       S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
		       S_00B22C_USER_SGPR(num_user_sgprs) |
		       S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
		       S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
		       S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
		       S_00B22C_LDS_SIZE(shader->config.lds_size));

	nparams = MAX2(shader->info.nr_param_exports, 1);
	shader->ctx_reg.ngg.spi_vs_out_config =
		S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
		S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);

	shader->ctx_reg.ngg.spi_shader_idx_format =
		S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
	shader->ctx_reg.ngg.spi_shader_pos_format =
		S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
		S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
					    V_02870C_SPI_SHADER_4COMP :
					    V_02870C_SPI_SHADER_NONE) |
		S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
					    V_02870C_SPI_SHADER_4COMP :
					    V_02870C_SPI_SHADER_NONE) |
		S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
					    V_02870C_SPI_SHADER_4COMP :
					    V_02870C_SPI_SHADER_NONE);

	shader->ctx_reg.ngg.vgt_primitiveid_en =
		S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
		S_028A84_NGG_DISABLE_PROVOK_REUSE(shader->key.mono.u.vs_export_prim_id ||
						  gs_sel->info.writes_primid);

	if (gs_type == PIPE_SHADER_GEOMETRY) {
		shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
		shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
	} else {
		shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
	}

	if (es_type == PIPE_SHADER_TESS_EVAL)
		si_set_tesseval_regs(sscreen, es_sel, pm4);

	shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
		S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
		S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
		S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
	shader->ctx_reg.ngg.ge_max_output_per_subgroup =
		S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
	shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
		S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
		S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
	shader->ctx_reg.ngg.vgt_gs_instance_cnt =
		S_028B90_CNT(gs_num_invocations) |
		S_028B90_ENABLE(gs_num_invocations > 1) |
		S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
			shader->ngg.max_vert_out_per_gs_instance);

	/* Always output hw-generated edge flags and pass them via the prim
	 * export to prevent drawing lines on internal edges of decomposed
	 * primitives (such as quads) with polygon mode = lines. Only VS needs
	 * this.
	 */
	shader->ctx_reg.ngg.pa_cl_ngg_cntl =
		S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX);
	shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(gs_sel, true);

	shader->ge_cntl =
		S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
		S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
		S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);

	/* Bug workaround for a possible hang with non-tessellation cases.
	 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
	 *
	 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
	 */
	if ((sscreen->info.family == CHIP_NAVI10 ||
	     sscreen->info.family == CHIP_NAVI12 ||
	     sscreen->info.family == CHIP_NAVI14) &&
	    (es_type == PIPE_SHADER_VERTEX || gs_type == PIPE_SHADER_VERTEX) && /* = no tess */
	    shader->ngg.hw_max_esverts != 256) {
		shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;

		if (shader->ngg.hw_max_esverts > 5) {
			shader->ge_cntl |=
				S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
		}
	}

	if (window_space) {
		shader->ctx_reg.ngg.pa_cl_vte_cntl =
			S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
	} else {
		shader->ctx_reg.ngg.pa_cl_vte_cntl =
			S_028818_VTX_W0_FMT(1) |
			S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
			S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
			S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
	}
}

static void si_emit_shader_vs(struct si_context *sctx)
{
	struct si_shader *shader = sctx->queued.named.vs->shader;
	unsigned initial_cdw = sctx->gfx_cs->current.cdw;

	if (!shader)
		return;

	radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
				   SI_TRACKED_VGT_GS_MODE,
				   shader->ctx_reg.vs.vgt_gs_mode);
	radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
				   SI_TRACKED_VGT_PRIMITIVEID_EN,
				   shader->ctx_reg.vs.vgt_primitiveid_en);

	if (sctx->chip_class <= GFX8) {
		radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
					   SI_TRACKED_VGT_REUSE_OFF,
					   shader->ctx_reg.vs.vgt_reuse_off);
	}

	radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
				   SI_TRACKED_SPI_VS_OUT_CONFIG,
				   shader->ctx_reg.vs.spi_vs_out_config);

	radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
				   SI_TRACKED_SPI_SHADER_POS_FORMAT,
				   shader->ctx_reg.vs.spi_shader_pos_format);

	radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
				   SI_TRACKED_PA_CL_VTE_CNTL,
				   shader->ctx_reg.vs.pa_cl_vte_cntl);

	if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
		radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
					   SI_TRACKED_VGT_TF_PARAM,
					   shader->vgt_tf_param);

	if (shader->vgt_vertex_reuse_block_cntl)
		radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
					   SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
					   shader->vgt_vertex_reuse_block_cntl);

	if (initial_cdw != sctx->gfx_cs->current.cdw)
		sctx->context_roll = true;

	/* Required programming for tessellation. (legacy pipeline only) */
	if (sctx->chip_class == GFX10 &&
	    shader->selector->type == PIPE_SHADER_TESS_EVAL) {
		radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
					   SI_TRACKED_VGT_GS_ONCHIP_CNTL,
					   S_028A44_ES_VERTS_PER_SUBGRP(250) |
					   S_028A44_GS_PRIMS_PER_SUBGRP(126) |
					   S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
	}

	if (sctx->chip_class >= GFX10) {
		radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
					       SI_TRACKED_PA_CL_VS_OUT_CNTL__VS,
					       shader->pa_cl_vs_out_cntl,
					       SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
	}
}

/**
 * Compute the state for \p shader, which will run as a vertex shader on the
 * hardware.
 *
 * If \p gs is non-NULL, it points to the geometry shader for which this shader
 * is the copy shader.
 */
static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
                         struct si_shader_selector *gs)
{
	const struct tgsi_shader_info *info = &shader->selector->info;
	struct si_pm4_state *pm4;
	unsigned num_user_sgprs, vgpr_comp_cnt;
	uint64_t va;
	unsigned nparams, oc_lds_en;
	unsigned window_space =
		info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
	bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;

	pm4 = si_get_shader_pm4_state(shader);
	if (!pm4)
		return;

	pm4->atom.emit = si_emit_shader_vs;

	/* We always write VGT_GS_MODE in the VS state, because every switch
	 * between different shader pipelines involving a different GS or no
	 * GS at all involves a switch of the VS (different GS use different
	 * copy shaders). On the other hand, when the API switches from a GS to
	 * no GS and then back to the same GS used originally, the GS state is
	 * not sent again.
	 */
	if (!gs) {
		unsigned mode = V_028A40_GS_OFF;

		/* PrimID needs GS scenario A. */
		if (enable_prim_id)
			mode = V_028A40_GS_SCENARIO_A;

		shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
		shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
	} else {
		shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
								sscreen->info.chip_class);
		shader->ctx_reg.vs.vgt_primitiveid_en = 0;
	}

	if (sscreen->info.chip_class <= GFX8) {
		/* Reuse needs to be set off if we write oViewport. */
		shader->ctx_reg.vs.vgt_reuse_off =
				S_028AB4_REUSE_OFF(info->writes_viewport_index);
	}

	va = shader->bo->gpu_address;
	si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);

	if (gs) {
		vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
		num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
	} else if (shader->selector->type == PIPE_SHADER_VERTEX) {
		vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, enable_prim_id);

		if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
			num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
					 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
		} else {
			num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
		}
	} else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
		vgpr_comp_cnt = enable_prim_id ? 3 : 2;
		num_user_sgprs = SI_TES_NUM_USER_SGPR;
	} else
		unreachable("invalid shader selector type");

	/* VS is required to export at least one param. */
	nparams = MAX2(shader->info.nr_param_exports, 1);
	shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);

	if (sscreen->info.chip_class >= GFX10) {
		shader->ctx_reg.vs.spi_vs_out_config |=
			S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
	}

	shader->ctx_reg.vs.spi_shader_pos_format =
			S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
			S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
						    V_02870C_SPI_SHADER_4COMP :
						    V_02870C_SPI_SHADER_NONE) |
			S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
						    V_02870C_SPI_SHADER_4COMP :
						    V_02870C_SPI_SHADER_NONE) |
			S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
						    V_02870C_SPI_SHADER_4COMP :
						    V_02870C_SPI_SHADER_NONE);
	shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(shader->selector, false);

	oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;

	si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
	si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));

	uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) /
					(sscreen->ge_wave_size == 32 ? 8 : 4)) |
			 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
			 S_00B128_DX10_CLAMP(1) |
			 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
			 S_00B128_FLOAT_MODE(shader->config.float_mode);
	uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) |
			 S_00B12C_OC_LDS_EN(oc_lds_en) |
			 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);

	if (sscreen->info.chip_class <= GFX9)
		rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);

	if (!sscreen->use_ngg_streamout) {
		rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
			 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
			 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
			 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
			 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
	}

	si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
	si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);

	if (window_space)
		shader->ctx_reg.vs.pa_cl_vte_cntl =
				S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
	else
		shader->ctx_reg.vs.pa_cl_vte_cntl =
				S_028818_VTX_W0_FMT(1) |
				S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
				S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
				S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);

	if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
		si_set_tesseval_regs(sscreen, shader->selector, pm4);

	polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
}

static unsigned si_get_ps_num_interp(struct si_shader *ps)
{
	struct tgsi_shader_info *info = &ps->selector->info;
	unsigned num_colors = !!(info->colors_read & 0x0f) +
			      !!(info->colors_read & 0xf0);
	unsigned num_interp = ps->selector->info.num_inputs +
			      (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);

	assert(num_interp <= 32);
	return MIN2(num_interp, 32);
}

static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
{
	unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
	unsigned i, num_targets = (util_last_bit(value) + 3) / 4;

	/* If the i-th target format is set, all previous target formats must
	 * be non-zero to avoid hangs.
	 */
	for (i = 0; i < num_targets; i++)
		if (!(value & (0xf << (i * 4))))
			value |= V_028714_SPI_SHADER_32_R << (i * 4);

	return value;
}

static void si_emit_shader_ps(struct si_context *sctx)
{
	struct si_shader *shader = sctx->queued.named.ps->shader;
	unsigned initial_cdw = sctx->gfx_cs->current.cdw;

	if (!shader)
		return;

	/* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
	radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
				    SI_TRACKED_SPI_PS_INPUT_ENA,
				    shader->ctx_reg.ps.spi_ps_input_ena,
				    shader->ctx_reg.ps.spi_ps_input_addr);

	radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
				   SI_TRACKED_SPI_BARYC_CNTL,
				   shader->ctx_reg.ps.spi_baryc_cntl);
	radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
				   SI_TRACKED_SPI_PS_IN_CONTROL,
				   shader->ctx_reg.ps.spi_ps_in_control);

	/* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
	radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
				    SI_TRACKED_SPI_SHADER_Z_FORMAT,
				    shader->ctx_reg.ps.spi_shader_z_format,
				    shader->ctx_reg.ps.spi_shader_col_format);

	radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
				   SI_TRACKED_CB_SHADER_MASK,
				   shader->ctx_reg.ps.cb_shader_mask);

	if (initial_cdw != sctx->gfx_cs->current.cdw)
		sctx->context_roll = true;
}

static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
{
	struct tgsi_shader_info *info = &shader->selector->info;
	struct si_pm4_state *pm4;
	unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
	unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
	uint64_t va;
	unsigned input_ena = shader->config.spi_ps_input_ena;

	/* we need to enable at least one of them, otherwise we hang the GPU */
	assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
	       G_0286CC_PERSP_CENTER_ENA(input_ena) ||
	       G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
	       G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
	       G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
	       G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
	       G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
	       G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
	/* POS_W_FLOAT_ENA requires one of the perspective weights. */
	assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
	       G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
	       G_0286CC_PERSP_CENTER_ENA(input_ena) ||
	       G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
	       G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));

	/* Validate interpolation optimization flags (read as implications). */
	assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
	       (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
		G_0286CC_PERSP_CENTROID_ENA(input_ena)));
	assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
	       (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
		G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
	assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
	       (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
		!G_0286CC_PERSP_CENTROID_ENA(input_ena)));
	assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
	       (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
		!G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
	assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
	       (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
		!G_0286CC_PERSP_CENTROID_ENA(input_ena)));
	assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
	       (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
		!G_0286CC_LINEAR_CENTROID_ENA(input_ena)));

	/* Validate cases when the optimizations are off (read as implications). */
	assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
	       !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
	       !G_0286CC_PERSP_CENTROID_ENA(input_ena));
	assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
	       !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
	       !G_0286CC_LINEAR_CENTROID_ENA(input_ena));

	pm4 = si_get_shader_pm4_state(shader);
	if (!pm4)
		return;

	pm4->atom.emit = si_emit_shader_ps;

	/* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
	 * Possible vaules:
	 * 0 -> Position = pixel center
	 * 1 -> Position = pixel centroid
	 * 2 -> Position = at sample position
	 *
	 * From GLSL 4.5 specification, section 7.1:
	 *   "The variable gl_FragCoord is available as an input variable from
	 *    within fragment shaders and it holds the window relative coordinates
	 *    (x, y, z, 1/w) values for the fragment. If multi-sampling, this
	 *    value can be for any location within the pixel, or one of the
	 *    fragment samples. The use of centroid does not further restrict
	 *    this value to be inside the current primitive."
	 *
	 * Meaning that centroid has no effect and we can return anything within
	 * the pixel. Thus, return the value at sample position, because that's
	 * the most accurate one shaders can get.
	 */
	spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);

	if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
	    TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
		spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);

	spi_shader_col_format = si_get_spi_shader_col_format(shader);
	cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);

	/* Ensure that some export memory is always allocated, for two reasons:
	 *
	 * 1) Correctness: The hardware ignores the EXEC mask if no export
	 *    memory is allocated, so KILL and alpha test do not work correctly
	 *    without this.
	 * 2) Performance: Every shader needs at least a NULL export, even when
	 *    it writes no color/depth output. The NULL export instruction
	 *    stalls without this setting.
	 *
	 * Don't add this to CB_SHADER_MASK.
	 *
	 * GFX10 supports pixel shaders without exports by setting both
	 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
	 * instructions if any are present.
	 */
	if ((sscreen->info.chip_class <= GFX9 ||
	     info->uses_kill ||
	     shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
	    !spi_shader_col_format &&
	    !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
		spi_shader_col_format = V_028714_SPI_SHADER_32_R;

	shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
	shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;

	/* Set interpolation controls. */
	spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
			    S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);

	shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
	shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
	shader->ctx_reg.ps.spi_shader_z_format =
			ac_get_spi_shader_z_format(info->writes_z,
						   info->writes_stencil,
						   info->writes_samplemask);
	shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
	shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;

	va = shader->bo->gpu_address;
	si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
	si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
	si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));

	uint32_t rsrc1 =
		S_00B028_VGPRS((shader->config.num_vgprs - 1) /
			       (sscreen->ps_wave_size == 32 ? 8 : 4)) |
		S_00B028_DX10_CLAMP(1) |
		S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
		S_00B028_FLOAT_MODE(shader->config.float_mode);

	if (sscreen->info.chip_class < GFX10) {
		rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
	}

	si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
	si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
		       S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
		       S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
		       S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
}

static void si_shader_init_pm4_state(struct si_screen *sscreen,
                                     struct si_shader *shader)
{
	switch (shader->selector->type) {
	case PIPE_SHADER_VERTEX:
		if (shader->key.as_ls)
			si_shader_ls(sscreen, shader);
		else if (shader->key.as_es)
			si_shader_es(sscreen, shader);
		else if (shader->key.as_ngg)
			gfx10_shader_ngg(sscreen, shader);
		else
			si_shader_vs(sscreen, shader, NULL);
		break;
	case PIPE_SHADER_TESS_CTRL:
		si_shader_hs(sscreen, shader);
		break;
	case PIPE_SHADER_TESS_EVAL:
		if (shader->key.as_es)
			si_shader_es(sscreen, shader);
		else if (shader->key.as_ngg)
			gfx10_shader_ngg(sscreen, shader);
		else
			si_shader_vs(sscreen, shader, NULL);
		break;
	case PIPE_SHADER_GEOMETRY:
		if (shader->key.as_ngg)
			gfx10_shader_ngg(sscreen, shader);
		else
			si_shader_gs(sscreen, shader);
		break;
	case PIPE_SHADER_FRAGMENT:
		si_shader_ps(sscreen, shader);
		break;
	default:
		assert(0);
	}
}

static unsigned si_get_alpha_test_func(struct si_context *sctx)
{
	/* Alpha-test should be disabled if colorbuffer 0 is integer. */
	return sctx->queued.named.dsa->alpha_func;
}

void si_shader_selector_key_vs(struct si_context *sctx,
			       struct si_shader_selector *vs,
			       struct si_shader_key *key,
			       struct si_vs_prolog_bits *prolog_key)
{
	if (!sctx->vertex_elements ||
	    vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD])
		return;

	struct si_vertex_elements *elts = sctx->vertex_elements;

	prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
	prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
	prolog_key->unpack_instance_id_from_vertex_id =
		sctx->prim_discard_cs_instancing;

	/* Prefer a monolithic shader to allow scheduling divisions around
	 * VBO loads. */
	if (prolog_key->instance_divisor_is_fetched)
		key->opt.prefer_mono = 1;

	unsigned count = MIN2(vs->info.num_inputs, elts->count);
	unsigned count_mask = (1 << count) - 1;
	unsigned fix = elts->fix_fetch_always & count_mask;
	unsigned opencode = elts->fix_fetch_opencode & count_mask;

	if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
		uint32_t mask = elts->fix_fetch_unaligned & count_mask;
		while (mask) {
			unsigned i = u_bit_scan(&mask);
			unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
			unsigned vbidx = elts->vertex_buffer_index[i];
			struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
			unsigned align_mask = (1 << log_hw_load_size) - 1;
			if (vb->buffer_offset & align_mask ||
			    vb->stride & align_mask) {
				fix |= 1 << i;
				opencode |= 1 << i;
			}
		}
	}

	while (fix) {
		unsigned i = u_bit_scan(&fix);
		key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
	}
	key->mono.vs_fetch_opencode = opencode;
}

static void si_shader_selector_key_hw_vs(struct si_context *sctx,
					 struct si_shader_selector *vs,
					 struct si_shader_key *key)
{
	struct si_shader_selector *ps = sctx->ps_shader.cso;

	key->opt.clip_disable =
		sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
		(vs->info.clipdist_writemask ||
		 vs->info.writes_clipvertex) &&
		!vs->info.culldist_writemask;

	/* Find out if PS is disabled. */
	bool ps_disabled = true;
	if (ps) {
		bool ps_modifies_zs = ps->info.uses_kill ||
				      ps->info.writes_z ||
				      ps->info.writes_stencil ||
				      ps->info.writes_samplemask ||
				      sctx->queued.named.blend->alpha_to_coverage ||
				      si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
		unsigned ps_colormask = si_get_total_colormask(sctx);

		ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
			      (!ps_colormask &&
			       !ps_modifies_zs &&
			       !ps->info.writes_memory);
	}

	/* Find out which VS outputs aren't used by the PS. */
	uint64_t outputs_written = vs->outputs_written_before_ps;
	uint64_t inputs_read = 0;

	/* Ignore outputs that are not passed from VS to PS. */
	outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
			     (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
			     (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));

	if (!ps_disabled) {
		inputs_read = ps->inputs_read;
	}

	uint64_t linked = outputs_written & inputs_read;

	key->opt.kill_outputs = ~linked & outputs_written;
}

/* Compute the key for the hw shader variant */
static inline void si_shader_selector_key(struct pipe_context *ctx,
					  struct si_shader_selector *sel,
					  union si_vgt_stages_key stages_key,
					  struct si_shader_key *key)
{
	struct si_context *sctx = (struct si_context *)ctx;

	memset(key, 0, sizeof(*key));

	switch (sel->type) {
	case PIPE_SHADER_VERTEX:
		si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);

		if (sctx->tes_shader.cso)
			key->as_ls = 1;
		else if (sctx->gs_shader.cso) {
			key->as_es = 1;
			key->as_ngg = stages_key.u.ngg;
		} else {
			key->as_ngg = stages_key.u.ngg;
			si_shader_selector_key_hw_vs(sctx, sel, key);

			if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
				key->mono.u.vs_export_prim_id = 1;
		}
		break;
	case PIPE_SHADER_TESS_CTRL:
		if (sctx->chip_class >= GFX9) {
			si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
						  key, &key->part.tcs.ls_prolog);
			key->part.tcs.ls = sctx->vs_shader.cso;

			/* When the LS VGPR fix is needed, monolithic shaders
			 * can:
			 *  - avoid initializing EXEC in both the LS prolog
			 *    and the LS main part when !vs_needs_prolog
			 *  - remove the fixup for unused input VGPRs
			 */
			key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;

			/* The LS output / HS input layout can be communicated
			 * directly instead of via user SGPRs for merged LS-HS.
			 * The LS VGPR fix prefers this too.
			 */
			key->opt.prefer_mono = 1;
		}

		key->part.tcs.epilog.prim_mode =
			sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
		key->part.tcs.epilog.invoc0_tess_factors_are_def =
			sel->tcs_info.tessfactors_are_def_in_all_invocs;
		key->part.tcs.epilog.tes_reads_tess_factors =
			sctx->tes_shader.cso->info.reads_tess_factors;

		if (sel == sctx->fixed_func_tcs_shader.cso)
			key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
		break;
	case PIPE_SHADER_TESS_EVAL:
		key->as_ngg = stages_key.u.ngg;

		if (sctx->gs_shader.cso)
			key->as_es = 1;
		else {
			si_shader_selector_key_hw_vs(sctx, sel, key);

			if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
				key->mono.u.vs_export_prim_id = 1;
		}
		break;
	case PIPE_SHADER_GEOMETRY:
		if (sctx->chip_class >= GFX9) {
			if (sctx->tes_shader.cso) {
				key->part.gs.es = sctx->tes_shader.cso;
			} else {
				si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
							  key, &key->part.gs.vs_prolog);
				key->part.gs.es = sctx->vs_shader.cso;
				key->part.gs.prolog.gfx9_prev_is_vs = 1;
			}

			key->as_ngg = stages_key.u.ngg;

			/* Merged ES-GS can have unbalanced wave usage.
			 *
			 * ES threads are per-vertex, while GS threads are
			 * per-primitive. So without any amplification, there
			 * are fewer GS threads than ES threads, which can result
			 * in empty (no-op) GS waves. With too much amplification,
			 * there are more GS threads than ES threads, which
			 * can result in empty (no-op) ES waves.
			 *
			 * Non-monolithic shaders are implemented by setting EXEC
			 * at the beginning of shader parts, and don't jump to
			 * the end if EXEC is 0.
			 *
			 * Monolithic shaders use conditional blocks, so they can
			 * jump and skip empty waves of ES or GS. So set this to
			 * always use optimized variants, which are monolithic.
			 */
			key->opt.prefer_mono = 1;
		}
		key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
		break;
	case PIPE_SHADER_FRAGMENT: {
		struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
		struct si_state_blend *blend = sctx->queued.named.blend;

		if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
		    sel->info.colors_written == 0x1)
			key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;

		/* Select the shader color format based on whether
		 * blending or alpha are needed.
		 */
		key->part.ps.epilog.spi_shader_col_format =
			(blend->blend_enable_4bit & blend->need_src_alpha_4bit &
			 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
			(blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
			 sctx->framebuffer.spi_shader_col_format_blend) |
			(~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
			 sctx->framebuffer.spi_shader_col_format_alpha) |
			(~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
			 sctx->framebuffer.spi_shader_col_format);
		key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;

		/* The output for dual source blending should have
		 * the same format as the first output.
		 */
		if (blend->dual_src_blend) {
			key->part.ps.epilog.spi_shader_col_format |=
				(key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
		}

		/* If alpha-to-coverage is enabled, we have to export alpha
		 * even if there is no color buffer.
		 */
		if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
		    blend->alpha_to_coverage)
			key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;

		/* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
		 * to the range supported by the type if a channel has less
		 * than 16 bits and the export format is 16_ABGR.
		 */
		if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
			key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
			key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
		}

		/* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
		if (!key->part.ps.epilog.last_cbuf) {
			key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
			key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
			key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
		}

		bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
		bool is_line = util_prim_is_lines(sctx->current_rast_prim);

		key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
		key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;

		key->part.ps.epilog.alpha_to_one = blend->alpha_to_one &&
						   rs->multisample_enable;

		key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
		key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
							   (is_line && rs->line_smooth)) &&
							  sctx->framebuffer.nr_samples <= 1;
		key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;

		if (sctx->ps_iter_samples > 1 &&
		    sel->info.reads_samplemask) {
			key->part.ps.prolog.samplemask_log_ps_iter =
				util_logbase2(sctx->ps_iter_samples);
		}

		if (rs->force_persample_interp &&
		    rs->multisample_enable &&
		    sctx->framebuffer.nr_samples > 1 &&
		    sctx->ps_iter_samples > 1) {
			key->part.ps.prolog.force_persp_sample_interp =
				sel->info.uses_persp_center ||
				sel->info.uses_persp_centroid;

			key->part.ps.prolog.force_linear_sample_interp =
				sel->info.uses_linear_center ||
				sel->info.uses_linear_centroid;
		} else if (rs->multisample_enable &&
			   sctx->framebuffer.nr_samples > 1) {
			key->part.ps.prolog.bc_optimize_for_persp =
				sel->info.uses_persp_center &&
				sel->info.uses_persp_centroid;
			key->part.ps.prolog.bc_optimize_for_linear =
				sel->info.uses_linear_center &&
				sel->info.uses_linear_centroid;
		} else {
			/* Make sure SPI doesn't compute more than 1 pair
			 * of (i,j), which is the optimization here. */
			key->part.ps.prolog.force_persp_center_interp =
				sel->info.uses_persp_center +
				sel->info.uses_persp_centroid +
				sel->info.uses_persp_sample > 1;

			key->part.ps.prolog.force_linear_center_interp =
				sel->info.uses_linear_center +
				sel->info.uses_linear_centroid +
				sel->info.uses_linear_sample > 1;

			if (sel->info.uses_persp_opcode_interp_sample ||
			    sel->info.uses_linear_opcode_interp_sample)
				key->mono.u.ps.interpolate_at_sample_force_center = 1;
		}

		key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);

		/* ps_uses_fbfetch is true only if the color buffer is bound. */
		if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
			struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
			struct pipe_resource *tex = cb0->texture;

			/* 1D textures are allocated and used as 2D on GFX9. */
			key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
			key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
						       (tex->target == PIPE_TEXTURE_1D ||
							tex->target == PIPE_TEXTURE_1D_ARRAY);
			key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
							 tex->target == PIPE_TEXTURE_2D_ARRAY ||
							 tex->target == PIPE_TEXTURE_CUBE ||
							 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
							 tex->target == PIPE_TEXTURE_3D;
		}
		break;
	}
	default:
		assert(0);
	}

	if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
		memset(&key->opt, 0, sizeof(key->opt));
}

static void si_build_shader_variant(struct si_shader *shader,
				    int thread_index,
				    bool low_priority)
{
	struct si_shader_selector *sel = shader->selector;
	struct si_screen *sscreen = sel->screen;
	struct ac_llvm_compiler *compiler;
	struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;

	if (thread_index >= 0) {
		if (low_priority) {
			assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
			compiler = &sscreen->compiler_lowp[thread_index];
		} else {
			assert(thread_index < ARRAY_SIZE(sscreen->compiler));
			compiler = &sscreen->compiler[thread_index];
		}
		if (!debug->async)
			debug = NULL;
	} else {
		assert(!low_priority);
		compiler = shader->compiler_ctx_state.compiler;
	}

	if (!compiler->passes)
		si_init_compiler(sscreen, compiler);

	if (unlikely(!si_shader_create(sscreen, compiler, shader, debug))) {
		PRINT_ERR("Failed to build shader variant (type=%u)\n",
			  sel->type);
		shader->compilation_failed = true;
		return;
	}

	if (shader->compiler_ctx_state.is_debug_context) {
		FILE *f = open_memstream(&shader->shader_log,
					 &shader->shader_log_size);
		if (f) {
			si_shader_dump(sscreen, shader, NULL, f, false);
			fclose(f);
		}
	}

	si_shader_init_pm4_state(sscreen, shader);
}

static void si_build_shader_variant_low_priority(void *job, int thread_index)
{
	struct si_shader *shader = (struct si_shader *)job;

	assert(thread_index >= 0);

	si_build_shader_variant(shader, thread_index, true);
}

static const struct si_shader_key zeroed;

static bool si_check_missing_main_part(struct si_screen *sscreen,
				       struct si_shader_selector *sel,
				       struct si_compiler_ctx_state *compiler_state,
				       struct si_shader_key *key)
{
	struct si_shader **mainp = si_get_main_shader_part(sel, key);

	if (!*mainp) {
		struct si_shader *main_part = CALLOC_STRUCT(si_shader);

		if (!main_part)
			return false;

		/* We can leave the fence as permanently signaled because the
		 * main part becomes visible globally only after it has been
		 * compiled. */
		util_queue_fence_init(&main_part->ready);

		main_part->selector = sel;
		main_part->key.as_es = key->as_es;
		main_part->key.as_ls = key->as_ls;
		main_part->key.as_ngg = key->as_ngg;
		main_part->is_monolithic = false;

		if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
					   main_part, &compiler_state->debug) != 0) {
			FREE(main_part);
			return false;
		}
		*mainp = main_part;
	}
	return true;
}

/**
 * Select a shader variant according to the shader key.
 *
 * \param optimized_or_none  If the key describes an optimized shader variant and
 *                           the compilation isn't finished, don't select any
 *                           shader and return an error.
 */
int si_shader_select_with_key(struct si_screen *sscreen,
			      struct si_shader_ctx_state *state,
			      struct si_compiler_ctx_state *compiler_state,
			      struct si_shader_key *key,
			      int thread_index,
			      bool optimized_or_none)
{
	struct si_shader_selector *sel = state->cso;
	struct si_shader_selector *previous_stage_sel = NULL;
	struct si_shader *current = state->current;
	struct si_shader *iter, *shader = NULL;

again:
	/* Check if we don't need to change anything.
	 * This path is also used for most shaders that don't need multiple
	 * variants, it will cost just a computation of the key and this
	 * test. */
	if (likely(current &&
		   memcmp(&current->key, key, sizeof(*key)) == 0)) {
		if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
			if (current->is_optimized) {
				if (optimized_or_none)
					return -1;

				memset(&key->opt, 0, sizeof(key->opt));
				goto current_not_ready;
			}

			util_queue_fence_wait(&current->ready);
		}

		return current->compilation_failed ? -1 : 0;
	}
current_not_ready:

	/* This must be done before the mutex is locked, because async GS
	 * compilation calls this function too, and therefore must enter
	 * the mutex first.
	 *
	 * Only wait if we are in a draw call. Don't wait if we are
	 * in a compiler thread.
	 */
	if (thread_index < 0)
		util_queue_fence_wait(&sel->ready);

	simple_mtx_lock(&sel->mutex);

	/* Find the shader variant. */
	for (iter = sel->first_variant; iter; iter = iter->next_variant) {
		/* Don't check the "current" shader. We checked it above. */
		if (current != iter &&
		    memcmp(&iter->key, key, sizeof(*key)) == 0) {
			simple_mtx_unlock(&sel->mutex);

			if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
				/* If it's an optimized shader and its compilation has
				 * been started but isn't done, use the unoptimized
				 * shader so as not to cause a stall due to compilation.
				 */
				if (iter->is_optimized) {
					if (optimized_or_none)
						return -1;
					memset(&key->opt, 0, sizeof(key->opt));
					goto again;
				}

				util_queue_fence_wait(&iter->ready);
			}

			if (iter->compilation_failed) {
				return -1; /* skip the draw call */
			}

			state->current = iter;
			return 0;
		}
	}

	/* Build a new shader. */
	shader = CALLOC_STRUCT(si_shader);
	if (!shader) {
		simple_mtx_unlock(&sel->mutex);
		return -ENOMEM;
	}

	util_queue_fence_init(&shader->ready);

	shader->selector = sel;
	shader->key = *key;
	shader->compiler_ctx_state = *compiler_state;

	/* If this is a merged shader, get the first shader's selector. */
	if (sscreen->info.chip_class >= GFX9) {
		if (sel->type == PIPE_SHADER_TESS_CTRL)
			previous_stage_sel = key->part.tcs.ls;
		else if (sel->type == PIPE_SHADER_GEOMETRY)
			previous_stage_sel = key->part.gs.es;

		/* We need to wait for the previous shader. */
		if (previous_stage_sel && thread_index < 0)
			util_queue_fence_wait(&previous_stage_sel->ready);
	}

	bool is_pure_monolithic =
		sscreen->use_monolithic_shaders ||
		memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;

	/* Compile the main shader part if it doesn't exist. This can happen
	 * if the initial guess was wrong.
	 *
	 * The prim discard CS doesn't need the main shader part.
	 */
	if (!is_pure_monolithic &&
	    !key->opt.vs_as_prim_discard_cs) {
		bool ok = true;

		/* Make sure the main shader part is present. This is needed
		 * for shaders that can be compiled as VS, LS, or ES, and only
		 * one of them is compiled at creation.
		 *
		 * It is also needed for GS, which can be compiled as non-NGG
		 * and NGG.
		 *
		 * For merged shaders, check that the starting shader's main
		 * part is present.
		 */
		if (previous_stage_sel) {
			struct si_shader_key shader1_key = zeroed;

			if (sel->type == PIPE_SHADER_TESS_CTRL) {
				shader1_key.as_ls = 1;
			} else if (sel->type == PIPE_SHADER_GEOMETRY) {
				shader1_key.as_es = 1;
				shader1_key.as_ngg = key->as_ngg; /* for Wave32 vs Wave64 */
			} else {
				assert(0);
			}

			simple_mtx_lock(&previous_stage_sel->mutex);
			ok = si_check_missing_main_part(sscreen,
							previous_stage_sel,
							compiler_state, &shader1_key);
			simple_mtx_unlock(&previous_stage_sel->mutex);
		}

		if (ok) {
			ok = si_check_missing_main_part(sscreen, sel,
							compiler_state, key);
		}

		if (!ok) {
			FREE(shader);
			simple_mtx_unlock(&sel->mutex);
			return -ENOMEM; /* skip the draw call */
		}
	}

	/* Keep the reference to the 1st shader of merged shaders, so that
	 * Gallium can't destroy it before we destroy the 2nd shader.
	 *
	 * Set sctx = NULL, because it's unused if we're not releasing
	 * the shader, and we don't have any sctx here.
	 */
	si_shader_selector_reference(NULL, &shader->previous_stage_sel,
				     previous_stage_sel);

	/* Monolithic-only shaders don't make a distinction between optimized
	 * and unoptimized. */
	shader->is_monolithic =
		is_pure_monolithic ||
		memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;

	/* The prim discard CS is always optimized. */
	shader->is_optimized =
		(!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
		 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;

	/* If it's an optimized shader, compile it asynchronously. */
	if (shader->is_optimized && thread_index < 0) {
		/* Compile it asynchronously. */
		util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
				   shader, &shader->ready,
				   si_build_shader_variant_low_priority, NULL,
				   0);

		/* Add only after the ready fence was reset, to guard against a
		 * race with si_bind_XX_shader. */
		if (!sel->last_variant) {
			sel->first_variant = shader;
			sel->last_variant = shader;
		} else {
			sel->last_variant->next_variant = shader;
			sel->last_variant = shader;
		}

		/* Use the default (unoptimized) shader for now. */
		memset(&key->opt, 0, sizeof(key->opt));
		simple_mtx_unlock(&sel->mutex);

		if (sscreen->options.sync_compile)
			util_queue_fence_wait(&shader->ready);

		if (optimized_or_none)
			return -1;
		goto again;
	}

	/* Reset the fence before adding to the variant list. */
	util_queue_fence_reset(&shader->ready);

	if (!sel->last_variant) {
		sel->first_variant = shader;
		sel->last_variant = shader;
	} else {
		sel->last_variant->next_variant = shader;
		sel->last_variant = shader;
	}

	simple_mtx_unlock(&sel->mutex);

	assert(!shader->is_optimized);
	si_build_shader_variant(shader, thread_index, false);

	util_queue_fence_signal(&shader->ready);

	if (!shader->compilation_failed)
		state->current = shader;

	return shader->compilation_failed ? -1 : 0;
}

static int si_shader_select(struct pipe_context *ctx,
			    struct si_shader_ctx_state *state,
			    union si_vgt_stages_key stages_key,
			    struct si_compiler_ctx_state *compiler_state)
{
	struct si_context *sctx = (struct si_context *)ctx;
	struct si_shader_key key;

	si_shader_selector_key(ctx, state->cso, stages_key, &key);
	return si_shader_select_with_key(sctx->screen, state, compiler_state,
					 &key, -1, false);
}

static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
					  bool streamout,
					  struct si_shader_key *key)
{
	unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];

	switch (info->processor) {
	case PIPE_SHADER_VERTEX:
		switch (next_shader) {
		case PIPE_SHADER_GEOMETRY:
			key->as_es = 1;
			break;
		case PIPE_SHADER_TESS_CTRL:
		case PIPE_SHADER_TESS_EVAL:
			key->as_ls = 1;
			break;
		default:
			/* If POSITION isn't written, it can only be a HW VS
			 * if streamout is used. If streamout isn't used,
			 * assume that it's a HW LS. (the next shader is TCS)
			 * This heuristic is needed for separate shader objects.
			 */
			if (!info->writes_position && !streamout)
				key->as_ls = 1;
		}
		break;

	case PIPE_SHADER_TESS_EVAL:
		if (next_shader == PIPE_SHADER_GEOMETRY ||
		    !info->writes_position)
			key->as_es = 1;
		break;
	}
}

/**
 * Compile the main shader part or the monolithic shader as part of
 * si_shader_selector initialization. Since it can be done asynchronously,
 * there is no way to report compile failures to applications.
 */
static void si_init_shader_selector_async(void *job, int thread_index)
{
	struct si_shader_selector *sel = (struct si_shader_selector *)job;
	struct si_screen *sscreen = sel->screen;
	struct ac_llvm_compiler *compiler;
	struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;

	assert(!debug->debug_message || debug->async);
	assert(thread_index >= 0);
	assert(thread_index < ARRAY_SIZE(sscreen->compiler));
	compiler = &sscreen->compiler[thread_index];

	if (!compiler->passes)
		si_init_compiler(sscreen, compiler);

	/* Serialize NIR to save memory. Monolithic shader variants
	 * have to deserialize NIR before compilation.
	 */
	if (sel->nir) {
		struct blob blob;
                size_t size;

		blob_init(&blob);
		/* true = remove optional debugging data to increase
		 * the likehood of getting more shader cache hits.
		 * It also drops variable names, so we'll save more memory.
		 */
		nir_serialize(&blob, sel->nir, true);
		blob_finish_get_buffer(&blob, &sel->nir_binary, &size);
		sel->nir_size = size;
	}

	/* Compile the main shader part for use with a prolog and/or epilog.
	 * If this fails, the driver will try to compile a monolithic shader
	 * on demand.
	 */
	if (!sscreen->use_monolithic_shaders) {
		struct si_shader *shader = CALLOC_STRUCT(si_shader);
		unsigned char ir_sha1_cache_key[20];

		if (!shader) {
			fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
			return;
		}

		/* We can leave the fence signaled because use of the default
		 * main part is guarded by the selector's ready fence. */
		util_queue_fence_init(&shader->ready);

		shader->selector = sel;
		shader->is_monolithic = false;
		si_parse_next_shader_property(&sel->info,
					      sel->so.num_outputs != 0,
					      &shader->key);

		if (sscreen->use_ngg &&
		    (!sel->so.num_outputs || sscreen->use_ngg_streamout) &&
		    ((sel->type == PIPE_SHADER_VERTEX && !shader->key.as_ls) ||
		     sel->type == PIPE_SHADER_TESS_EVAL ||
		     sel->type == PIPE_SHADER_GEOMETRY))
			shader->key.as_ngg = 1;

		if (sel->tokens || sel->nir) {
			si_get_ir_cache_key(sel, shader->key.as_ngg,
					    shader->key.as_es, ir_sha1_cache_key);
		}

		/* Try to load the shader from the shader cache. */
		simple_mtx_lock(&sscreen->shader_cache_mutex);

		if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) {
			simple_mtx_unlock(&sscreen->shader_cache_mutex);
			si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
		} else {
			simple_mtx_unlock(&sscreen->shader_cache_mutex);

			/* Compile the shader if it hasn't been loaded from the cache. */
			if (si_compile_tgsi_shader(sscreen, compiler, shader,
						   debug) != 0) {
				FREE(shader);
				fprintf(stderr, "radeonsi: can't compile a main shader part\n");
				return;
			}

			simple_mtx_lock(&sscreen->shader_cache_mutex);
			si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key,
						      shader, true);
			simple_mtx_unlock(&sscreen->shader_cache_mutex);
		}

		*si_get_main_shader_part(sel, &shader->key) = shader;

		/* Unset "outputs_written" flags for outputs converted to
		 * DEFAULT_VAL, so that later inter-shader optimizations don't
		 * try to eliminate outputs that don't exist in the final
		 * shader.
		 *
		 * This is only done if non-monolithic shaders are enabled.
		 */
		if ((sel->type == PIPE_SHADER_VERTEX ||
		     sel->type == PIPE_SHADER_TESS_EVAL) &&
		    !shader->key.as_ls &&
		    !shader->key.as_es) {
			unsigned i;

			for (i = 0; i < sel->info.num_outputs; i++) {
				unsigned offset = shader->info.vs_output_param_offset[i];

				if (offset <= AC_EXP_PARAM_OFFSET_31)
					continue;

				unsigned name = sel->info.output_semantic_name[i];
				unsigned index = sel->info.output_semantic_index[i];
				unsigned id;

				switch (name) {
				case TGSI_SEMANTIC_GENERIC:
					/* don't process indices the function can't handle */
					if (index >= SI_MAX_IO_GENERIC)
						break;
					/* fall through */
				default:
					id = si_shader_io_get_unique_index(name, index, true);
					sel->outputs_written_before_ps &= ~(1ull << id);
					break;
				case TGSI_SEMANTIC_POSITION: /* ignore these */
				case TGSI_SEMANTIC_PSIZE:
				case TGSI_SEMANTIC_CLIPVERTEX:
				case TGSI_SEMANTIC_EDGEFLAG:
					break;
				}
			}
		}
	}

	/* The GS copy shader is always pre-compiled. */
	if (sel->type == PIPE_SHADER_GEOMETRY &&
	    (!sscreen->use_ngg ||
	     !sscreen->use_ngg_streamout || /* also for PRIMITIVES_GENERATED */
	     sel->tess_turns_off_ngg)) {
		sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
		if (!sel->gs_copy_shader) {
			fprintf(stderr, "radeonsi: can't create GS copy shader\n");
			return;
		}

		si_shader_vs(sscreen, sel->gs_copy_shader, sel);
	}

	/* Free NIR. We only keep serialized NIR after this point. */
	if (sel->nir) {
		ralloc_free(sel->nir);
		sel->nir = NULL;
	}
}

void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
				 struct util_queue_fence *ready_fence,
				 struct si_compiler_ctx_state *compiler_ctx_state,
				 void *job, util_queue_execute_func execute)
{
	util_queue_fence_init(ready_fence);

	struct util_async_debug_callback async_debug;
	bool debug =
		(sctx->debug.debug_message && !sctx->debug.async) ||
		sctx->is_debug ||
		si_can_dump_shader(sctx->screen, processor);

	if (debug) {
		u_async_debug_init(&async_debug);
		compiler_ctx_state->debug = async_debug.base;
	}

	util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
			   ready_fence, execute, NULL, 0);

	if (debug) {
		util_queue_fence_wait(ready_fence);
		u_async_debug_drain(&async_debug, &sctx->debug);
		u_async_debug_cleanup(&async_debug);
	}

	if (sctx->screen->options.sync_compile)
		util_queue_fence_wait(ready_fence);
}

/* Return descriptor slot usage masks from the given shader info. */
void si_get_active_slot_masks(const struct tgsi_shader_info *info,
			      uint32_t *const_and_shader_buffers,
			      uint64_t *samplers_and_images)
{
	unsigned start, num_shaderbufs, num_constbufs, num_images, num_msaa_images, num_samplers;

	num_shaderbufs = util_last_bit(info->shader_buffers_declared);
	num_constbufs = util_last_bit(info->const_buffers_declared);
	/* two 8-byte images share one 16-byte slot */
	num_images = align(util_last_bit(info->images_declared), 2);
	num_msaa_images = align(util_last_bit(info->msaa_images_declared), 2);
	num_samplers = util_last_bit(info->samplers_declared);

	/* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
	start = si_get_shaderbuf_slot(num_shaderbufs - 1);
	*const_and_shader_buffers =
		u_bit_consecutive(start, num_shaderbufs + num_constbufs);

	/* The layout is:
	 *   - fmask[last] ... fmask[0]     go to [15-last .. 15]
	 *   - image[last] ... image[0]     go to [31-last .. 31]
	 *   - sampler[0] ... sampler[last] go to [32 .. 32+last*2]
	 *
	 * FMASKs for images are placed separately, because MSAA images are rare,
	 * and so we can benefit from a better cache hit rate if we keep image
	 * descriptors together.
	 */
	if (num_msaa_images)
		num_images = SI_NUM_IMAGES + num_msaa_images; /* add FMASK descriptors */

	start = si_get_image_slot(num_images - 1) / 2;
	*samplers_and_images =
		u_bit_consecutive64(start, num_images / 2 + num_samplers);
}

static void *si_create_shader_selector(struct pipe_context *ctx,
				       const struct pipe_shader_state *state)
{
	struct si_screen *sscreen = (struct si_screen *)ctx->screen;
	struct si_context *sctx = (struct si_context*)ctx;
	struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
	int i;

	if (!sel)
		return NULL;

	pipe_reference_init(&sel->reference, 1);
	sel->screen = sscreen;
	sel->compiler_ctx_state.debug = sctx->debug;
	sel->compiler_ctx_state.is_debug_context = sctx->is_debug;

	sel->so = state->stream_output;

	if (state->type == PIPE_SHADER_IR_TGSI &&
	    !sscreen->options.enable_nir) {
		sel->tokens = tgsi_dup_tokens(state->tokens);
		if (!sel->tokens) {
			FREE(sel);
			return NULL;
		}

		tgsi_scan_shader(state->tokens, &sel->info);
		tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);

		/* Fixup for TGSI: Set which opcode uses which (i,j) pair. */
		if (sel->info.uses_persp_opcode_interp_centroid)
			sel->info.uses_persp_centroid = true;

		if (sel->info.uses_linear_opcode_interp_centroid)
			sel->info.uses_linear_centroid = true;

		if (sel->info.uses_persp_opcode_interp_offset ||
		    sel->info.uses_persp_opcode_interp_sample)
			sel->info.uses_persp_center = true;

		if (sel->info.uses_linear_opcode_interp_offset ||
		    sel->info.uses_linear_opcode_interp_sample)
			sel->info.uses_linear_center = true;
	} else {
		if (state->type == PIPE_SHADER_IR_TGSI) {
			sel->nir = tgsi_to_nir(state->tokens, ctx->screen);
		} else {
			assert(state->type == PIPE_SHADER_IR_NIR);
			sel->nir = state->ir.nir;
		}

		si_nir_scan_shader(sel->nir, &sel->info);
		si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info);
		si_nir_adjust_driver_locations(sel->nir);
	}

	sel->type = sel->info.processor;
	p_atomic_inc(&sscreen->num_shaders_created);
	si_get_active_slot_masks(&sel->info,
				 &sel->active_const_and_shader_buffers,
				 &sel->active_samplers_and_images);

	/* Record which streamout buffers are enabled. */
	for (i = 0; i < sel->so.num_outputs; i++) {
		sel->enabled_streamout_buffer_mask |=
			(1 << sel->so.output[i].output_buffer) <<
			(sel->so.output[i].stream * 4);
	}

	/* The prolog is a no-op if there are no inputs. */
	sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
			       sel->info.num_inputs &&
			       !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];

	sel->force_correct_derivs_after_kill =
		sel->type == PIPE_SHADER_FRAGMENT &&
		sel->info.uses_derivatives &&
		sel->info.uses_kill &&
		sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);

	sel->prim_discard_cs_allowed =
		sel->type == PIPE_SHADER_VERTEX &&
		!sel->info.uses_bindless_images &&
		!sel->info.uses_bindless_samplers &&
		!sel->info.writes_memory &&
		!sel->info.writes_viewport_index &&
		!sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
		!sel->so.num_outputs;

	switch (sel->type) {
	case PIPE_SHADER_GEOMETRY:
		sel->gs_output_prim =
			sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];

		/* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
		sel->rast_prim = sel->gs_output_prim;
		if (util_rast_prim_is_triangles(sel->rast_prim))
			sel->rast_prim = PIPE_PRIM_TRIANGLES;

		sel->gs_max_out_vertices =
			sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
		sel->gs_num_invocations =
			sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
		sel->gsvs_vertex_size = sel->info.num_outputs * 16;
		sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
					  sel->gs_max_out_vertices;

		sel->max_gs_stream = 0;
		for (i = 0; i < sel->so.num_outputs; i++)
			sel->max_gs_stream = MAX2(sel->max_gs_stream,
						  sel->so.output[i].stream);

		sel->gs_input_verts_per_prim =
			u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);

		/* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
		sel->tess_turns_off_ngg =
			sscreen->info.chip_class == GFX10 &&
			sel->gs_num_invocations * sel->gs_max_out_vertices > 256;
		break;

	case PIPE_SHADER_TESS_CTRL:
		/* Always reserve space for these. */
		sel->patch_outputs_written |=
			(1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
			(1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
		/* fall through */
	case PIPE_SHADER_VERTEX:
	case PIPE_SHADER_TESS_EVAL:
		for (i = 0; i < sel->info.num_outputs; i++) {
			unsigned name = sel->info.output_semantic_name[i];
			unsigned index = sel->info.output_semantic_index[i];

			switch (name) {
			case TGSI_SEMANTIC_TESSINNER:
			case TGSI_SEMANTIC_TESSOUTER:
			case TGSI_SEMANTIC_PATCH:
				sel->patch_outputs_written |=
					1ull << si_shader_io_get_unique_index_patch(name, index);
				break;

			case TGSI_SEMANTIC_GENERIC:
				/* don't process indices the function can't handle */
				if (index >= SI_MAX_IO_GENERIC)
					break;
				/* fall through */
			default:
				sel->outputs_written |=
					1ull << si_shader_io_get_unique_index(name, index, false);
				sel->outputs_written_before_ps |=
					1ull << si_shader_io_get_unique_index(name, index, true);
				break;
			case TGSI_SEMANTIC_EDGEFLAG:
				break;
			}
		}
		sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
		sel->lshs_vertex_stride = sel->esgs_itemsize;

		/* Add 1 dword to reduce LDS bank conflicts, so that each vertex
		 * will start on a different bank. (except for the maximum 32*16).
		 */
		if (sel->lshs_vertex_stride < 32*16)
			sel->lshs_vertex_stride += 4;

		/* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
		 * conflicts, i.e. each vertex will start at a different bank.
		 */
		if (sctx->chip_class >= GFX9)
			sel->esgs_itemsize += 4;

		assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);

		/* Only for TES: */
		if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
			sel->rast_prim = PIPE_PRIM_POINTS;
		else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
			sel->rast_prim = PIPE_PRIM_LINE_STRIP;
		else
			sel->rast_prim = PIPE_PRIM_TRIANGLES;
		break;

	case PIPE_SHADER_FRAGMENT:
		for (i = 0; i < sel->info.num_inputs; i++) {
			unsigned name = sel->info.input_semantic_name[i];
			unsigned index = sel->info.input_semantic_index[i];

			switch (name) {
			case TGSI_SEMANTIC_GENERIC:
				/* don't process indices the function can't handle */
				if (index >= SI_MAX_IO_GENERIC)
					break;
				/* fall through */
			default:
				sel->inputs_read |=
					1ull << si_shader_io_get_unique_index(name, index, true);
				break;
			case TGSI_SEMANTIC_PCOORD: /* ignore this */
				break;
			}
		}

		for (i = 0; i < 8; i++)
			if (sel->info.colors_written & (1 << i))
				sel->colors_written_4bit |= 0xf << (4 * i);

		for (i = 0; i < sel->info.num_inputs; i++) {
			if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
				int index = sel->info.input_semantic_index[i];
				sel->color_attr_index[index] = i;
			}
		}
		break;
	default:;
	}

	/* PA_CL_VS_OUT_CNTL */
	if (sctx->chip_class <= GFX9)
		sel->pa_cl_vs_out_cntl = si_get_vs_out_cntl(sel, false);

	sel->clipdist_mask = sel->info.writes_clipvertex ?
				     SIX_BITS : sel->info.clipdist_writemask;
	sel->culldist_mask = sel->info.culldist_writemask <<
			     sel->info.num_written_clipdistance;

	/* DB_SHADER_CONTROL */
	sel->db_shader_control =
		S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
		S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
		S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
		S_02880C_KILL_ENABLE(sel->info.uses_kill);

	switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
	case TGSI_FS_DEPTH_LAYOUT_GREATER:
		sel->db_shader_control |=
			S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
		break;
	case TGSI_FS_DEPTH_LAYOUT_LESS:
		sel->db_shader_control |=
			S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
		break;
	}

	/* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
	 *
	 *   | early Z/S | writes_mem | allow_ReZ? |      Z_ORDER       | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
	 * --|-----------|------------|------------|--------------------|-------------------|-------------
	 * 1a|   false   |   false    |   true     | EarlyZ_Then_ReZ    |         0         |     0
	 * 1b|   false   |   false    |   false    | EarlyZ_Then_LateZ  |         0         |     0
	 * 2 |   false   |   true     |   n/a      |       LateZ        |         1         |     0
	 * 3 |   true    |   false    |   n/a      | EarlyZ_Then_LateZ  |         0         |     0
	 * 4 |   true    |   true     |   n/a      | EarlyZ_Then_LateZ  |         0         |     1
	 *
	 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
	 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
	 *
	 * Don't use ReZ without profiling !!!
	 *
	 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
	 * shaders.
	 */
	if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
		/* Cases 3, 4. */
		sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
					  S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
					  S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
	} else if (sel->info.writes_memory) {
		/* Case 2. */
		sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
					  S_02880C_EXEC_ON_HIER_FAIL(1);
	} else {
		/* Case 1. */
		sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
	}

	if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
		sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);

	(void) simple_mtx_init(&sel->mutex, mtx_plain);

	si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
				    &sel->compiler_ctx_state, sel,
				    si_init_shader_selector_async);
	return sel;
}

static void si_update_streamout_state(struct si_context *sctx)
{
	struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;

	if (!shader_with_so)
		return;

	sctx->streamout.enabled_stream_buffers_mask =
		shader_with_so->enabled_streamout_buffer_mask;
	sctx->streamout.stride_in_dw = shader_with_so->so.stride;
}

static void si_update_clip_regs(struct si_context *sctx,
				struct si_shader_selector *old_hw_vs,
				struct si_shader *old_hw_vs_variant,
				struct si_shader_selector *next_hw_vs,
				struct si_shader *next_hw_vs_variant)
{
	if (next_hw_vs &&
	    (!old_hw_vs ||
	     old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
	     next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
	     old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
	     old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
	     old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
	     !old_hw_vs_variant ||
	     !next_hw_vs_variant ||
	     old_hw_vs_variant->key.opt.clip_disable !=
	     next_hw_vs_variant->key.opt.clip_disable))
		si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
}

static void si_update_common_shader_state(struct si_context *sctx)
{
	sctx->uses_bindless_samplers =
		si_shader_uses_bindless_samplers(sctx->vs_shader.cso)  ||
		si_shader_uses_bindless_samplers(sctx->gs_shader.cso)  ||
		si_shader_uses_bindless_samplers(sctx->ps_shader.cso)  ||
		si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
		si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
	sctx->uses_bindless_images =
		si_shader_uses_bindless_images(sctx->vs_shader.cso)  ||
		si_shader_uses_bindless_images(sctx->gs_shader.cso)  ||
		si_shader_uses_bindless_images(sctx->ps_shader.cso)  ||
		si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
		si_shader_uses_bindless_images(sctx->tes_shader.cso);
	sctx->do_update_shaders = true;
}

static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
{
	struct si_context *sctx = (struct si_context *)ctx;
	struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
	struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
	struct si_shader_selector *sel = state;

	if (sctx->vs_shader.cso == sel)
		return;

	sctx->vs_shader.cso = sel;
	sctx->vs_shader.current = sel ? sel->first_variant : NULL;
	sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] : 0;

	if (si_update_ngg(sctx))
		si_shader_change_notify(sctx);

	si_update_common_shader_state(sctx);
	si_update_vs_viewport_state(sctx);
	si_set_active_descriptors_for_shader(sctx, sel);
	si_update_streamout_state(sctx);
	si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
			    si_get_vs(sctx)->cso, si_get_vs_state(sctx));
}

static void si_update_tess_uses_prim_id(struct si_context *sctx)
{
	sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
		(sctx->tes_shader.cso &&
		 sctx->tes_shader.cso->info.uses_primid) ||
		(sctx->tcs_shader.cso &&
		 sctx->tcs_shader.cso->info.uses_primid) ||
		(sctx->gs_shader.cso &&
		 sctx->gs_shader.cso->info.uses_primid) ||
		(sctx->ps_shader.cso && !sctx->gs_shader.cso &&
		 sctx->ps_shader.cso->info.uses_primid);
}

bool si_update_ngg(struct si_context *sctx)
{
	if (!sctx->screen->use_ngg) {
		assert(!sctx->ngg);
		return false;
	}

	bool new_ngg = true;

	if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
	    sctx->gs_shader.cso->tess_turns_off_ngg) {
		new_ngg = false;
	} else if (!sctx->screen->use_ngg_streamout) {
		struct si_shader_selector *last = si_get_vs(sctx)->cso;

		if ((last && last->so.num_outputs) ||
		    sctx->streamout.prims_gen_query_enabled)
			new_ngg = false;
	}

	if (new_ngg != sctx->ngg) {
		/* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
		 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
		 * pointers are set.
		 */
		if ((sctx->family == CHIP_NAVI10 ||
		     sctx->family == CHIP_NAVI12 ||
		     sctx->family == CHIP_NAVI14) &&
		    !new_ngg)
			sctx->flags |= SI_CONTEXT_VGT_FLUSH;

		sctx->ngg = new_ngg;
		sctx->last_rast_prim = -1; /* reset this so that it gets updated */
		return true;
	}
	return false;
}

static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
{
	struct si_context *sctx = (struct si_context *)ctx;
	struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
	struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
	struct si_shader_selector *sel = state;
	bool enable_changed = !!sctx->gs_shader.cso != !!sel;
	bool ngg_changed;

	if (sctx->gs_shader.cso == sel)
		return;

	sctx->gs_shader.cso = sel;
	sctx->gs_shader.current = sel ? sel->first_variant : NULL;
	sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;

	si_update_common_shader_state(sctx);
	sctx->last_rast_prim = -1; /* reset this so that it gets updated */

	ngg_changed = si_update_ngg(sctx);
	if (ngg_changed || enable_changed)
		si_shader_change_notify(sctx);
	if (enable_changed) {
		if (sctx->ia_multi_vgt_param_key.u.uses_tess)
			si_update_tess_uses_prim_id(sctx);
	}
	si_update_vs_viewport_state(sctx);
	si_set_active_descriptors_for_shader(sctx, sel);
	si_update_streamout_state(sctx);
	si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
			    si_get_vs(sctx)->cso, si_get_vs_state(sctx));
}

static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
{
	struct si_context *sctx = (struct si_context *)ctx;
	struct si_shader_selector *sel = state;
	bool enable_changed = !!sctx->tcs_shader.cso != !!sel;

	if (sctx->tcs_shader.cso == sel)
		return;

	sctx->tcs_shader.cso = sel;
	sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
	si_update_tess_uses_prim_id(sctx);

	si_update_common_shader_state(sctx);

	if (enable_changed)
		sctx->last_tcs = NULL; /* invalidate derived tess state */

	si_set_active_descriptors_for_shader(sctx, sel);
}

static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
{
	struct si_context *sctx = (struct si_context *)ctx;
	struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
	struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
	struct si_shader_selector *sel = state;
	bool enable_changed = !!sctx->tes_shader.cso != !!sel;

	if (sctx->tes_shader.cso == sel)
		return;

	sctx->tes_shader.cso = sel;
	sctx->tes_shader.current = sel ? sel->first_variant : NULL;
	sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
	si_update_tess_uses_prim_id(sctx);

	si_update_common_shader_state(sctx);
	sctx->last_rast_prim = -1; /* reset this so that it gets updated */

	bool ngg_changed = si_update_ngg(sctx);
	if (ngg_changed || enable_changed)
		si_shader_change_notify(sctx);
	if (enable_changed)
		sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
	si_update_vs_viewport_state(sctx);
	si_set_active_descriptors_for_shader(sctx, sel);
	si_update_streamout_state(sctx);
	si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
			    si_get_vs(sctx)->cso, si_get_vs_state(sctx));
}

static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
{
	struct si_context *sctx = (struct si_context *)ctx;
	struct si_shader_selector *old_sel = sctx->ps_shader.cso;
	struct si_shader_selector *sel = state;

	/* skip if supplied shader is one already in use */
	if (old_sel == sel)
		return;

	sctx->ps_shader.cso = sel;
	sctx->ps_shader.current = sel ? sel->first_variant : NULL;

	si_update_common_shader_state(sctx);
	if (sel) {
		if (sctx->ia_multi_vgt_param_key.u.uses_tess)
			si_update_tess_uses_prim_id(sctx);

		if (!old_sel ||
		    old_sel->info.colors_written != sel->info.colors_written)
			si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);

		if (sctx->screen->has_out_of_order_rast &&
		    (!old_sel ||
		     old_sel->info.writes_memory != sel->info.writes_memory ||
		     old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
		     sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
			si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
	}
	si_set_active_descriptors_for_shader(sctx, sel);
	si_update_ps_colorbuf0_slot(sctx);
}

static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
{
	if (shader->is_optimized) {
		util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
				    &shader->ready);
	}

	util_queue_fence_destroy(&shader->ready);

	if (shader->pm4) {
		/* If destroyed shaders were not unbound, the next compiled
		 * shader variant could get the same pointer address and so
		 * binding it to the same shader stage would be considered
		 * a no-op, causing random behavior.
		 */
		switch (shader->selector->type) {
		case PIPE_SHADER_VERTEX:
			if (shader->key.as_ls) {
				assert(sctx->chip_class <= GFX8);
				si_pm4_delete_state(sctx, ls, shader->pm4);
			} else if (shader->key.as_es) {
				assert(sctx->chip_class <= GFX8);
				si_pm4_delete_state(sctx, es, shader->pm4);
			} else if (shader->key.as_ngg) {
				si_pm4_delete_state(sctx, gs, shader->pm4);
			} else {
				si_pm4_delete_state(sctx, vs, shader->pm4);
			}
			break;
		case PIPE_SHADER_TESS_CTRL:
			si_pm4_delete_state(sctx, hs, shader->pm4);
			break;
		case PIPE_SHADER_TESS_EVAL:
			if (shader->key.as_es) {
				assert(sctx->chip_class <= GFX8);
				si_pm4_delete_state(sctx, es, shader->pm4);
			} else if (shader->key.as_ngg) {
				si_pm4_delete_state(sctx, gs, shader->pm4);
			} else {
				si_pm4_delete_state(sctx, vs, shader->pm4);
			}
			break;
		case PIPE_SHADER_GEOMETRY:
			if (shader->is_gs_copy_shader)
				si_pm4_delete_state(sctx, vs, shader->pm4);
			else
				si_pm4_delete_state(sctx, gs, shader->pm4);
			break;
		case PIPE_SHADER_FRAGMENT:
			si_pm4_delete_state(sctx, ps, shader->pm4);
			break;
		default:;
		}
	}

	si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
	si_shader_destroy(shader);
	free(shader);
}

void si_destroy_shader_selector(struct si_context *sctx,
				struct si_shader_selector *sel)
{
	struct si_shader *p = sel->first_variant, *c;
	struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
		[PIPE_SHADER_VERTEX] = &sctx->vs_shader,
		[PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
		[PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
		[PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
		[PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
	};

	util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);

	if (current_shader[sel->type]->cso == sel) {
		current_shader[sel->type]->cso = NULL;
		current_shader[sel->type]->current = NULL;
	}

	while (p) {
		c = p->next_variant;
		si_delete_shader(sctx, p);
		p = c;
	}

	if (sel->main_shader_part)
		si_delete_shader(sctx, sel->main_shader_part);
	if (sel->main_shader_part_ls)
		si_delete_shader(sctx, sel->main_shader_part_ls);
	if (sel->main_shader_part_es)
		si_delete_shader(sctx, sel->main_shader_part_es);
	if (sel->main_shader_part_ngg)
		si_delete_shader(sctx, sel->main_shader_part_ngg);
	if (sel->gs_copy_shader)
		si_delete_shader(sctx, sel->gs_copy_shader);

	util_queue_fence_destroy(&sel->ready);
	simple_mtx_destroy(&sel->mutex);
	free(sel->tokens);
	ralloc_free(sel->nir);
	free(sel->nir_binary);
	free(sel);
}

static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
{
	struct si_context *sctx = (struct si_context *)ctx;
	struct si_shader_selector *sel = (struct si_shader_selector *)state;

	si_shader_selector_reference(sctx, &sel, NULL);
}

static unsigned si_get_ps_input_cntl(struct si_context *sctx,
				     struct si_shader *vs, unsigned name,
				     unsigned index, unsigned interpolate)
{
	struct tgsi_shader_info *vsinfo = &vs->selector->info;
	unsigned j, offset, ps_input_cntl = 0;

	if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
	    (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
	    name == TGSI_SEMANTIC_PRIMID)
		ps_input_cntl |= S_028644_FLAT_SHADE(1);

	if (name == TGSI_SEMANTIC_PCOORD ||
	    (name == TGSI_SEMANTIC_TEXCOORD &&
	     sctx->sprite_coord_enable & (1 << index))) {
		ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
	}

	for (j = 0; j < vsinfo->num_outputs; j++) {
		if (name == vsinfo->output_semantic_name[j] &&
		    index == vsinfo->output_semantic_index[j]) {
			offset = vs->info.vs_output_param_offset[j];

			if (offset <= AC_EXP_PARAM_OFFSET_31) {
				/* The input is loaded from parameter memory. */
				ps_input_cntl |= S_028644_OFFSET(offset);
			} else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
				if (offset == AC_EXP_PARAM_UNDEFINED) {
					/* This can happen with depth-only rendering. */
					offset = 0;
				} else {
					/* The input is a DEFAULT_VAL constant. */
					assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
					       offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
					offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
				}

				ps_input_cntl = S_028644_OFFSET(0x20) |
						S_028644_DEFAULT_VAL(offset);
			}
			break;
		}
	}

	if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
		/* PrimID is written after the last output when HW VS is used. */
		ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
	else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
		/* No corresponding output found, load defaults into input.
		 * Don't set any other bits.
		 * (FLAT_SHADE=1 completely changes behavior) */
		ps_input_cntl = S_028644_OFFSET(0x20);
		/* D3D 9 behaviour. GL is undefined */
		if (name == TGSI_SEMANTIC_COLOR && index == 0)
			ps_input_cntl |= S_028644_DEFAULT_VAL(3);
	}
	return ps_input_cntl;
}

static void si_emit_spi_map(struct si_context *sctx)
{
	struct si_shader *ps = sctx->ps_shader.current;
	struct si_shader *vs = si_get_vs_state(sctx);
	struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
	unsigned i, num_interp, num_written = 0, bcol_interp[2];
	unsigned spi_ps_input_cntl[32];

	if (!ps || !ps->selector->info.num_inputs)
		return;

	num_interp = si_get_ps_num_interp(ps);
	assert(num_interp > 0);

	for (i = 0; i < psinfo->num_inputs; i++) {
		unsigned name = psinfo->input_semantic_name[i];
		unsigned index = psinfo->input_semantic_index[i];
		unsigned interpolate = psinfo->input_interpolate[i];

		spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
							    index, interpolate);

		if (name == TGSI_SEMANTIC_COLOR) {
			assert(index < ARRAY_SIZE(bcol_interp));
			bcol_interp[index] = interpolate;
		}
	}

	if (ps->key.part.ps.prolog.color_two_side) {
		unsigned bcol = TGSI_SEMANTIC_BCOLOR;

		for (i = 0; i < 2; i++) {
			if (!(psinfo->colors_read & (0xf << (i * 4))))
				continue;

			spi_ps_input_cntl[num_written++] =
			  si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);

		}
	}
	assert(num_interp == num_written);

	/* R_028644_SPI_PS_INPUT_CNTL_0 */
	/* Dota 2: Only ~16% of SPI map updates set different values. */
	/* Talos: Only ~9% of SPI map updates set different values. */
	unsigned initial_cdw = sctx->gfx_cs->current.cdw;
	radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
				    spi_ps_input_cntl,
				    sctx->tracked_regs.spi_ps_input_cntl, num_interp);

	if (initial_cdw != sctx->gfx_cs->current.cdw)
		sctx->context_roll = true;
}

/**
 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
 */
static void si_init_config_add_vgt_flush(struct si_context *sctx)
{
	if (sctx->init_config_has_vgt_flush)
		return;

	/* Done by Vulkan before VGT_FLUSH. */
	si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
	si_pm4_cmd_add(sctx->init_config,
		       EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
	si_pm4_cmd_end(sctx->init_config, false);

	/* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
	si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
	si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
	si_pm4_cmd_end(sctx->init_config, false);
	sctx->init_config_has_vgt_flush = true;
}

/* Initialize state related to ESGS / GSVS ring buffers */
static bool si_update_gs_ring_buffers(struct si_context *sctx)
{
	struct si_shader_selector *es =
		sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
	struct si_shader_selector *gs = sctx->gs_shader.cso;
	struct si_pm4_state *pm4;

	/* Chip constants. */
	unsigned num_se = sctx->screen->info.max_se;
	unsigned wave_size = 64;
	unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
	/* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
	 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
	 */
	unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
	unsigned alignment = 256 * num_se;
	/* The maximum size is 63.999 MB per SE. */
	unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;

	/* Calculate the minimum size. */
	unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
					    wave_size, alignment);

	/* These are recommended sizes, not minimum sizes. */
	unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
				  es->esgs_itemsize * gs->gs_input_verts_per_prim;
	unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
				  gs->max_gsvs_emit_size;

	min_esgs_ring_size = align(min_esgs_ring_size, alignment);
	esgs_ring_size = align(esgs_ring_size, alignment);
	gsvs_ring_size = align(gsvs_ring_size, alignment);

	esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
	gsvs_ring_size = MIN2(gsvs_ring_size, max_size);

	/* Some rings don't have to be allocated if shaders don't use them.
	 * (e.g. no varyings between ES and GS or GS and VS)
	 *
	 * GFX9 doesn't have the ESGS ring.
	 */
	bool update_esgs = sctx->chip_class <= GFX8 &&
			   esgs_ring_size &&
			   (!sctx->esgs_ring ||
			    sctx->esgs_ring->width0 < esgs_ring_size);
	bool update_gsvs = gsvs_ring_size &&
			   (!sctx->gsvs_ring ||
			    sctx->gsvs_ring->width0 < gsvs_ring_size);

	if (!update_esgs && !update_gsvs)
		return true;

	if (update_esgs) {
		pipe_resource_reference(&sctx->esgs_ring, NULL);
		sctx->esgs_ring =
			pipe_aligned_buffer_create(sctx->b.screen,
						   SI_RESOURCE_FLAG_UNMAPPABLE,
						   PIPE_USAGE_DEFAULT,
						   esgs_ring_size,
						   sctx->screen->info.pte_fragment_size);
		if (!sctx->esgs_ring)
			return false;
	}

	if (update_gsvs) {
		pipe_resource_reference(&sctx->gsvs_ring, NULL);
		sctx->gsvs_ring =
			pipe_aligned_buffer_create(sctx->b.screen,
						   SI_RESOURCE_FLAG_UNMAPPABLE,
						   PIPE_USAGE_DEFAULT,
						   gsvs_ring_size,
						   sctx->screen->info.pte_fragment_size);
		if (!sctx->gsvs_ring)
			return false;
	}

	/* Create the "init_config_gs_rings" state. */
	pm4 = CALLOC_STRUCT(si_pm4_state);
	if (!pm4)
		return false;

	if (sctx->chip_class >= GFX7) {
		if (sctx->esgs_ring) {
			assert(sctx->chip_class <= GFX8);
			si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
				       sctx->esgs_ring->width0 / 256);
		}
		if (sctx->gsvs_ring)
			si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
				       sctx->gsvs_ring->width0 / 256);
	} else {
		if (sctx->esgs_ring)
			si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
				       sctx->esgs_ring->width0 / 256);
		if (sctx->gsvs_ring)
			si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
				       sctx->gsvs_ring->width0 / 256);
	}

	/* Set the state. */
	if (sctx->init_config_gs_rings)
		si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
	sctx->init_config_gs_rings = pm4;

	if (!sctx->init_config_has_vgt_flush) {
		si_init_config_add_vgt_flush(sctx);
		si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
	}

	/* Flush the context to re-emit both init_config states. */
	sctx->initial_gfx_cs_size = 0; /* force flush */
	si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);

	/* Set ring bindings. */
	if (sctx->esgs_ring) {
		assert(sctx->chip_class <= GFX8);
		si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
				   sctx->esgs_ring, 0, sctx->esgs_ring->width0,
				   true, true, 4, 64, 0);
		si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
				   sctx->esgs_ring, 0, sctx->esgs_ring->width0,
				   false, false, 0, 0, 0);
	}
	if (sctx->gsvs_ring) {
		si_set_ring_buffer(sctx, SI_RING_GSVS,
				   sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
				   false, false, 0, 0, 0);
	}

	return true;
}

static void si_shader_lock(struct si_shader *shader)
{
	simple_mtx_lock(&shader->selector->mutex);
	if (shader->previous_stage_sel) {
		assert(shader->previous_stage_sel != shader->selector);
		simple_mtx_lock(&shader->previous_stage_sel->mutex);
	}
}

static void si_shader_unlock(struct si_shader *shader)
{
	if (shader->previous_stage_sel)
		simple_mtx_unlock(&shader->previous_stage_sel->mutex);
	simple_mtx_unlock(&shader->selector->mutex);
}

/**
 * @returns 1 if \p sel has been updated to use a new scratch buffer
 *          0 if not
 *          < 0 if there was a failure
 */
static int si_update_scratch_buffer(struct si_context *sctx,
				    struct si_shader *shader)
{
	uint64_t scratch_va = sctx->scratch_buffer->gpu_address;

	if (!shader)
		return 0;

	/* This shader doesn't need a scratch buffer */
	if (shader->config.scratch_bytes_per_wave == 0)
		return 0;

	/* Prevent race conditions when updating:
	 * - si_shader::scratch_bo
	 * - si_shader::binary::code
	 * - si_shader::previous_stage::binary::code.
	 */
	si_shader_lock(shader);

	/* This shader is already configured to use the current
	 * scratch buffer. */
	if (shader->scratch_bo == sctx->scratch_buffer) {
		si_shader_unlock(shader);
		return 0;
	}

	assert(sctx->scratch_buffer);

	/* Replace the shader bo with a new bo that has the relocs applied. */
	if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
		si_shader_unlock(shader);
		return -1;
	}

	/* Update the shader state to use the new shader bo. */
	si_shader_init_pm4_state(sctx->screen, shader);

	si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);

	si_shader_unlock(shader);
	return 1;
}

static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
{
	return shader ? shader->config.scratch_bytes_per_wave : 0;
}

static struct si_shader *si_get_tcs_current(struct si_context *sctx)
{
	if (!sctx->tes_shader.cso)
		return NULL; /* tessellation disabled */

	return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
				      sctx->fixed_func_tcs_shader.current;
}

static bool si_update_scratch_relocs(struct si_context *sctx)
{
	struct si_shader *tcs = si_get_tcs_current(sctx);
	int r;

	/* Update the shaders, so that they are using the latest scratch.
	 * The scratch buffer may have been changed since these shaders were
	 * last used, so we still need to try to update them, even if they
	 * require scratch buffers smaller than the current size.
	 */
	r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
	if (r < 0)
		return false;
	if (r == 1)
		si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);

	r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
	if (r < 0)
		return false;
	if (r == 1)
		si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);

	r = si_update_scratch_buffer(sctx, tcs);
	if (r < 0)
		return false;
	if (r == 1)
		si_pm4_bind_state(sctx, hs, tcs->pm4);

	/* VS can be bound as LS, ES, or VS. */
	r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
	if (r < 0)
		return false;
	if (r == 1) {
		if (sctx->vs_shader.current->key.as_ls)
			si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
		else if (sctx->vs_shader.current->key.as_es)
			si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
		else if (sctx->vs_shader.current->key.as_ngg)
			si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
		else
			si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
	}

	/* TES can be bound as ES or VS. */
	r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
	if (r < 0)
		return false;
	if (r == 1) {
		if (sctx->tes_shader.current->key.as_es)
			si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
		else if (sctx->tes_shader.current->key.as_ngg)
			si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
		else
			si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
	}

	return true;
}

static bool si_update_spi_tmpring_size(struct si_context *sctx)
{
	/* SPI_TMPRING_SIZE.WAVESIZE must be constant for each scratch buffer.
	 * There are 2 cases to handle:
	 *
	 * - If the current needed size is less than the maximum seen size,
	 *   use the maximum seen size, so that WAVESIZE remains the same.
	 *
	 * - If the current needed size is greater than the maximum seen size,
	 *   the scratch buffer is reallocated, so we can increase WAVESIZE.
	 *
	 * Shaders that set SCRATCH_EN=0 don't allocate scratch space.
	 * Otherwise, the number of waves that can use scratch is
	 * SPI_TMPRING_SIZE.WAVES.
	 */
	unsigned bytes = 0;

	bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
	bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
	bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));

	if (sctx->tes_shader.cso) {
		bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
		bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(si_get_tcs_current(sctx)));
	}

	sctx->max_seen_scratch_bytes_per_wave =
		MAX2(sctx->max_seen_scratch_bytes_per_wave, bytes);

	unsigned scratch_needed_size =
		sctx->max_seen_scratch_bytes_per_wave * sctx->scratch_waves;
	unsigned spi_tmpring_size;

	if (scratch_needed_size > 0) {
		if (!sctx->scratch_buffer ||
		    scratch_needed_size > sctx->scratch_buffer->b.b.width0) {
			/* Create a bigger scratch buffer */
			si_resource_reference(&sctx->scratch_buffer, NULL);

			sctx->scratch_buffer =
				si_aligned_buffer_create(&sctx->screen->b,
							 SI_RESOURCE_FLAG_UNMAPPABLE,
							 PIPE_USAGE_DEFAULT,
							 scratch_needed_size,
							 sctx->screen->info.pte_fragment_size);
			if (!sctx->scratch_buffer)
				return false;

			si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
			si_context_add_resource_size(sctx,
						     &sctx->scratch_buffer->b.b);
		}

		if (!si_update_scratch_relocs(sctx))
			return false;
	}

	/* The LLVM shader backend should be reporting aligned scratch_sizes. */
	assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
		"scratch size should already be aligned correctly.");

	spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
			   S_0286E8_WAVESIZE(sctx->max_seen_scratch_bytes_per_wave >> 10);
	if (spi_tmpring_size != sctx->spi_tmpring_size) {
		sctx->spi_tmpring_size = spi_tmpring_size;
		si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
	}
	return true;
}

static void si_init_tess_factor_ring(struct si_context *sctx)
{
	assert(!sctx->tess_rings);
	assert(((sctx->screen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);

	/* The address must be aligned to 2^19, because the shader only
	 * receives the high 13 bits.
	 */
	sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
						    SI_RESOURCE_FLAG_32BIT,
						    PIPE_USAGE_DEFAULT,
						    sctx->screen->tess_offchip_ring_size +
						    sctx->screen->tess_factor_ring_size,
						    1 << 19);
	if (!sctx->tess_rings)
		return;

	si_init_config_add_vgt_flush(sctx);

	si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
		      RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);

	uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
			     sctx->screen->tess_offchip_ring_size;

	/* Append these registers to the init config state. */
	if (sctx->chip_class >= GFX7) {
		si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
			       S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
		si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
			       factor_va >> 8);
		if (sctx->chip_class >= GFX10)
			si_pm4_set_reg(sctx->init_config, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
				       S_030984_BASE_HI(factor_va >> 40));
		else if (sctx->chip_class == GFX9)
			si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
				       S_030944_BASE_HI(factor_va >> 40));
		si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
			       sctx->screen->vgt_hs_offchip_param);
	} else {
		si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
			       S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
		si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
			       factor_va >> 8);
		si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
		               sctx->screen->vgt_hs_offchip_param);
	}

	/* Flush the context to re-emit the init_config state.
	 * This is done only once in a lifetime of a context.
	 */
	si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
	sctx->initial_gfx_cs_size = 0; /* force flush */
	si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
}

static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
						       union si_vgt_stages_key key)
{
	struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
	uint32_t stages = 0;

	if (key.u.tess) {
		stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
		          S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);

		if (key.u.gs)
			stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
				  S_028B54_GS_EN(1);
		else if (key.u.ngg)
			stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
		else
			stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
	} else if (key.u.gs) {
		stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
			  S_028B54_GS_EN(1);
	} else if (key.u.ngg) {
		stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
	}

	if (key.u.ngg) {
		stages |= S_028B54_PRIMGEN_EN(1) |
			  S_028B54_NGG_WAVE_ID_EN(key.u.streamout) |
			  S_028B54_PRIMGEN_PASSTHRU_EN(key.u.ngg_passthrough);
	} else if (key.u.gs)
		stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);

	if (screen->info.chip_class >= GFX9)
		stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);

	if (screen->info.chip_class >= GFX10 && screen->ge_wave_size == 32) {
		stages |= S_028B54_HS_W32_EN(1) |
			  S_028B54_GS_W32_EN(key.u.ngg) | /* legacy GS only supports Wave64 */
			  S_028B54_VS_W32_EN(1);
	}

	si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
	return pm4;
}

static void si_update_vgt_shader_config(struct si_context *sctx,
					union si_vgt_stages_key key)
{
	struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];

	if (unlikely(!*pm4))
		*pm4 = si_build_vgt_shader_config(sctx->screen, key);
	si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
}

bool si_update_shaders(struct si_context *sctx)
{
	struct pipe_context *ctx = (struct pipe_context*)sctx;
	struct si_compiler_ctx_state compiler_state;
	struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
	struct si_shader *old_vs = si_get_vs_state(sctx);
	bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
	struct si_shader *old_ps = sctx->ps_shader.current;
	union si_vgt_stages_key key;
	unsigned old_spi_shader_col_format =
		old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
	int r;

	if (!sctx->compiler.passes)
		si_init_compiler(sctx->screen, &sctx->compiler);

	compiler_state.compiler = &sctx->compiler;
	compiler_state.debug = sctx->debug;
	compiler_state.is_debug_context = sctx->is_debug;

	key.index = 0;

	if (sctx->tes_shader.cso)
		key.u.tess = 1;
	if (sctx->gs_shader.cso)
		key.u.gs = 1;

	if (sctx->ngg) {
		key.u.ngg = 1;
		key.u.streamout = !!si_get_vs(sctx)->cso->so.num_outputs;
	}

	/* Update TCS and TES. */
	if (sctx->tes_shader.cso) {
		if (!sctx->tess_rings) {
			si_init_tess_factor_ring(sctx);
			if (!sctx->tess_rings)
				return false;
		}

		if (sctx->tcs_shader.cso) {
			r = si_shader_select(ctx, &sctx->tcs_shader, key,
					     &compiler_state);
			if (r)
				return false;
			si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
		} else {
			if (!sctx->fixed_func_tcs_shader.cso) {
				sctx->fixed_func_tcs_shader.cso =
					si_create_fixed_func_tcs(sctx);
				if (!sctx->fixed_func_tcs_shader.cso)
					return false;
			}

			r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
					     key, &compiler_state);
			if (r)
				return false;
			si_pm4_bind_state(sctx, hs,
					  sctx->fixed_func_tcs_shader.current->pm4);
		}

		if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
			r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
			if (r)
				return false;

			if (sctx->gs_shader.cso) {
				/* TES as ES */
				assert(sctx->chip_class <= GFX8);
				si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
			} else if (key.u.ngg) {
				si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
			} else {
				si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
			}
		}
	} else {
		if (sctx->chip_class <= GFX8)
			si_pm4_bind_state(sctx, ls, NULL);
		si_pm4_bind_state(sctx, hs, NULL);
	}

	/* Update GS. */
	if (sctx->gs_shader.cso) {
		r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
		if (r)
			return false;
		si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
		if (!key.u.ngg) {
			si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);

			if (!si_update_gs_ring_buffers(sctx))
				return false;
		} else {
			si_pm4_bind_state(sctx, vs, NULL);
		}
	} else {
		if (!key.u.ngg) {
			si_pm4_bind_state(sctx, gs, NULL);
			if (sctx->chip_class <= GFX8)
				si_pm4_bind_state(sctx, es, NULL);
		}
	}

	/* Update VS. */
	if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
		r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
		if (r)
			return false;

		if (!key.u.tess && !key.u.gs) {
			if (key.u.ngg) {
				si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
				si_pm4_bind_state(sctx, vs, NULL);
			} else {
				si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
			}
		} else if (sctx->tes_shader.cso) {
			si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
		} else {
			assert(sctx->gs_shader.cso);
			si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
		}
	}

	/* This must be done after the shader variant is selected. */
	if (sctx->ngg)
		key.u.ngg_passthrough = gfx10_is_ngg_passthrough(si_get_vs(sctx)->current);

	si_update_vgt_shader_config(sctx, key);

	if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
		si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);

	if (sctx->ps_shader.cso) {
		unsigned db_shader_control;

		r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
		if (r)
			return false;
		si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);

		db_shader_control =
			sctx->ps_shader.cso->db_shader_control |
			S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);

		if (si_pm4_state_changed(sctx, ps) ||
		    si_pm4_state_changed(sctx, vs) ||
		    (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
		    sctx->sprite_coord_enable != rs->sprite_coord_enable ||
		    sctx->flatshade != rs->flatshade) {
			sctx->sprite_coord_enable = rs->sprite_coord_enable;
			sctx->flatshade = rs->flatshade;
			si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
		}

		if (sctx->screen->info.rbplus_allowed &&
		    si_pm4_state_changed(sctx, ps) &&
		    (!old_ps ||
		     old_spi_shader_col_format !=
		     sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
			si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);

		if (sctx->ps_db_shader_control != db_shader_control) {
			sctx->ps_db_shader_control = db_shader_control;
			si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
			if (sctx->screen->dpbb_allowed)
				si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
		}

		if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
			sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
			si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);

			if (sctx->chip_class == GFX6)
				si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);

			if (sctx->framebuffer.nr_samples <= 1)
				si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
		}
	}

	if (si_pm4_state_enabled_and_changed(sctx, ls) ||
	    si_pm4_state_enabled_and_changed(sctx, hs) ||
	    si_pm4_state_enabled_and_changed(sctx, es) ||
	    si_pm4_state_enabled_and_changed(sctx, gs) ||
	    si_pm4_state_enabled_and_changed(sctx, vs) ||
	    si_pm4_state_enabled_and_changed(sctx, ps)) {
		if (!si_update_spi_tmpring_size(sctx))
			return false;
	}

	if (sctx->chip_class >= GFX7) {
		if (si_pm4_state_enabled_and_changed(sctx, ls))
			sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
		else if (!sctx->queued.named.ls)
			sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;

		if (si_pm4_state_enabled_and_changed(sctx, hs))
			sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
		else if (!sctx->queued.named.hs)
			sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;

		if (si_pm4_state_enabled_and_changed(sctx, es))
			sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
		else if (!sctx->queued.named.es)
			sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;

		if (si_pm4_state_enabled_and_changed(sctx, gs))
			sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
		else if (!sctx->queued.named.gs)
			sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;

		if (si_pm4_state_enabled_and_changed(sctx, vs))
			sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
		else if (!sctx->queued.named.vs)
			sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;

		if (si_pm4_state_enabled_and_changed(sctx, ps))
			sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
		else if (!sctx->queued.named.ps)
			sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
	}

	sctx->do_update_shaders = false;
	return true;
}

static void si_emit_scratch_state(struct si_context *sctx)
{
	struct radeon_cmdbuf *cs = sctx->gfx_cs;

	radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
			       sctx->spi_tmpring_size);

	if (sctx->scratch_buffer) {
		radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
				      sctx->scratch_buffer, RADEON_USAGE_READWRITE,
				      RADEON_PRIO_SCRATCH_BUFFER);
	}
}

void si_init_shader_functions(struct si_context *sctx)
{
	sctx->atoms.s.spi_map.emit = si_emit_spi_map;
	sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;

	sctx->b.create_vs_state = si_create_shader_selector;
	sctx->b.create_tcs_state = si_create_shader_selector;
	sctx->b.create_tes_state = si_create_shader_selector;
	sctx->b.create_gs_state = si_create_shader_selector;
	sctx->b.create_fs_state = si_create_shader_selector;

	sctx->b.bind_vs_state = si_bind_vs_shader;
	sctx->b.bind_tcs_state = si_bind_tcs_shader;
	sctx->b.bind_tes_state = si_bind_tes_shader;
	sctx->b.bind_gs_state = si_bind_gs_shader;
	sctx->b.bind_fs_state = si_bind_ps_shader;

	sctx->b.delete_vs_state = si_delete_shader_selector;
	sctx->b.delete_tcs_state = si_delete_shader_selector;
	sctx->b.delete_tes_state = si_delete_shader_selector;
	sctx->b.delete_gs_state = si_delete_shader_selector;
	sctx->b.delete_fs_state = si_delete_shader_selector;
}