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<?xml version="1.0" encoding="UTF-8"?>
<!--
Copyright © 2020 Google, Inc.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice (including the next
paragraph) shall be included in all copies or substantial portions of the
Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
-->
<!--
The basic idea is to define a hierarchy of encodings, where various
ranges of bits can be either:
* patterns to match to select a sub-encoding (0, 1, x (dontcare))
* instruction parameters (ie. dst register, type, etc)
* range of bits that delegates to another hierarchy (ie. src reg
encoding which has multiple sub-encodings depending on gpr/const/
relative)
The root of the encoding hierarchy defines the size. By the concrete
leaf nodes of an encoding hierarchy all bits should be accounted for
(ie. either defined fields or as 0/1/x).
TODO:
* add optional min/max gen fields for cases where same binary maps
to different instructions and/or encodings on later gens
* schema
-->
<isa>
<import file="ir3-common.xml"/>
<bitset name="#instruction" size="64">
<doc>
Encoding of an ir3 instruction. All instructions are 64b.
</doc>
<gen min="300"/>
<encode type="struct ir3_instruction *" case-prefix="OPC_">
<!--
Define mapping from encode src to individual fields,
which are common across all instruction categories
at the root instruction level
Not all of these apply to all instructions, but we
can define mappings here for anything that is used
in more than one instruction category. For things
that are specific to a single instruction category,
mappings should be defined at that level instead.
-->
<map name="DST">src->regs[0]</map>
<map name="SRC1">src->regs[1]</map>
<map name="SRC2">src->regs[2]</map>
<map name="SRC3">src->regs[3]</map>
<map name="REPEAT">src->repeat</map>
<map name="SS">!!(src->flags & IR3_INSTR_SS)</map>
<map name="JP">!!(src->flags & IR3_INSTR_JP)</map>
<map name="SY">!!(src->flags & IR3_INSTR_SY)</map>
<map name="UL">!!(src->flags & IR3_INSTR_UL)</map>
<map name="EQ">0</map> <!-- We don't use this (yet) -->
<map name="SAT">!!(src->flags & IR3_INSTR_SAT)</map>
</encode>
</bitset>
<import file="ir3-cat0.xml"/>
<import file="ir3-cat1.xml"/>
<import file="ir3-cat2.xml"/>
<import file="ir3-cat3.xml"/>
<import file="ir3-cat4.xml"/>
<import file="ir3-cat5.xml"/>
<import file="ir3-cat6.xml"/>
<import file="ir3-cat7.xml"/>
</isa>
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