From 74f9f3937a074d2e385ada45f7fb76a453a6d099 Mon Sep 17 00:00:00 2001 From: Erik Faye-Lund Date: Wed, 21 Apr 2021 12:30:23 +0200 Subject: zink: emit cap early We have enough information to emit this cap early, so let's do that. Reviewed-By: Mike Blumenkrantz Part-of: --- src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'src/gallium') diff --git a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c index a55adf15d8d..7ebfa408768 100644 --- a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c +++ b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c @@ -2586,8 +2586,6 @@ emit_intrinsic(struct ntv_context *ctx, nir_intrinsic_instr *intr) break; case nir_intrinsic_load_sample_mask_in: - if (ctx->info->fs.post_depth_coverage) - spirv_builder_emit_cap(&ctx->builder, SpvCapabilitySampleMaskPostDepthCoverage); emit_load_uint_input(ctx, intr, &ctx->sample_mask_in_var, "gl_SampleMaskIn", SpvBuiltInSampleMask); break; @@ -3581,6 +3579,12 @@ nir_to_spirv(struct nir_shader *s, const struct zink_so_info *so_info, bool spir spirv_builder_emit_cap(&ctx.builder, SpvCapabilitySampledBuffer); switch (s->info.stage) { + case MESA_SHADER_FRAGMENT: + if (s->info.fs.post_depth_coverage && + BITSET_TEST(s->info.system_values_read, SYSTEM_VALUE_SAMPLE_MASK_IN)) + spirv_builder_emit_cap(&ctx.builder, SpvCapabilitySampleMaskPostDepthCoverage); + break; + case MESA_SHADER_TESS_CTRL: case MESA_SHADER_TESS_EVAL: spirv_builder_emit_cap(&ctx.builder, SpvCapabilityTessellation); -- cgit v1.2.3