From c0538860bf656a1796b4a5c9c136c7d3517dfba6 Mon Sep 17 00:00:00 2001 From: José Fonseca Date: Mon, 22 Apr 2013 15:28:32 +0100 Subject: gallivm: Fix assignment of unsigned values to OUT register. TEMP is not the only register file that accept unsigned. OUT too. Actually, what determines the appropriate type of the destination value is not the opcode, but rather the register. Also cleanup/simplify code. Add a few more asserts, but also make code more robust by handling graceful if assert fails. This fixes segfault / assertion in the included vert-uadd.sh graw shader. Reviewed-by: Roland Scheidegger --- src/gallium/tests/graw/vertex-shader/vert-uadd.sh | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100755 src/gallium/tests/graw/vertex-shader/vert-uadd.sh (limited to 'src/gallium/tests') diff --git a/src/gallium/tests/graw/vertex-shader/vert-uadd.sh b/src/gallium/tests/graw/vertex-shader/vert-uadd.sh new file mode 100755 index 00000000000..d2a7a1b0aea --- /dev/null +++ b/src/gallium/tests/graw/vertex-shader/vert-uadd.sh @@ -0,0 +1,9 @@ +VERT +DCL IN[0] +DCL IN[1] +DCL OUT[0], GENERIC[0] +DCL OUT[1], GENERIC[1] +IMM[0] INT32 {1, 0, 0, 0} +MOV OUT[0], IN[0] +UADD OUT[1].x, IN[1].xxxx, IMM[0].xxxx +END -- cgit v1.2.3