From d40a3212aee2c0b2667011f28540cecf000bdea3 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 15 Nov 2016 15:47:49 -0800 Subject: vc4: Add a note for the future about texture latency calculation. Debugging a shader-db reported cycle count regression from the tex coalescing, I eventually figured out that the texture latencies were totally bogus. Really fixing it will probably involve mirroring vc4_qir_schedule.c's texture fifo management here. --- src/gallium/drivers/vc4/vc4_qpu_schedule.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'src/gallium/drivers/vc4') diff --git a/src/gallium/drivers/vc4/vc4_qpu_schedule.c b/src/gallium/drivers/vc4/vc4_qpu_schedule.c index 45360f73410..878cdf95d96 100644 --- a/src/gallium/drivers/vc4/vc4_qpu_schedule.c +++ b/src/gallium/drivers/vc4/vc4_qpu_schedule.c @@ -705,6 +705,26 @@ static uint32_t waddr_latency(uint32_t waddr, uint64_t after) /* Apply some huge latency between texture fetch requests and getting * their results back. + * + * FIXME: This is actually pretty bogus. If we do: + * + * mov tmu0_s, a + * + * mov tmu0_s, b + * load_tmu0 + * + * load_tmu0 + * + * we count that as worse than + * + * mov tmu0_s, a + * mov tmu0_s, b + * + * load_tmu0 + * + * load_tmu0 + * + * because we associate the first load_tmu0 with the *second* tmu0_s. */ if (waddr == QPU_W_TMU0_S) { if (QPU_GET_FIELD(after, QPU_SIG) == QPU_SIG_LOAD_TMU0) -- cgit v1.2.3