From f1d2b373177dbbb582cefb0d6c88994073fab652 Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Fri, 10 Aug 2012 12:06:37 -0300 Subject: i965: make GT3 machines work as GT3 instead of GT2 We were not allowed to say the "GT3" name, but we really needed to have the PCI IDs because too many people had such machines, so we had to make the GT3 machines work as GT2. Let's just say that GT2_PLUS was a short for GT2_PLUS_1 :) NOTE: This is a candidate for stable branches. Signed-off-by: Paulo Zanoni Signed-off-by: Kenneth Graunke --- include/pci_ids/i965_pci_ids.h | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'include/pci_ids') diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h index 9a2da61357e..3e9765c6026 100644 --- a/include/pci_ids/i965_pci_ids.h +++ b/include/pci_ids/i965_pci_ids.h @@ -28,40 +28,40 @@ CHIPSET(0x015a, IVYBRIDGE_S_GT1, ivb_gt1) CHIPSET(0x016a, IVYBRIDGE_S_GT2, ivb_gt2) CHIPSET(0x0402, HASWELL_GT1, hsw_gt1) CHIPSET(0x0412, HASWELL_GT2, hsw_gt2) -CHIPSET(0x0422, HASWELL_GT2_PLUS, hsw_gt2) +CHIPSET(0x0422, HASWELL_GT3, hsw_gt3) CHIPSET(0x0406, HASWELL_M_GT1, hsw_gt1) CHIPSET(0x0416, HASWELL_M_GT2, hsw_gt2) -CHIPSET(0x0426, HASWELL_M_GT2_PLUS, hsw_gt2) +CHIPSET(0x0426, HASWELL_M_GT3, hsw_gt3) CHIPSET(0x040A, HASWELL_S_GT1, hsw_gt1) CHIPSET(0x041A, HASWELL_S_GT2, hsw_gt2) -CHIPSET(0x042A, HASWELL_S_GT2_PLUS, hsw_gt2) +CHIPSET(0x042A, HASWELL_S_GT3, hsw_gt3) CHIPSET(0x0C02, HASWELL_SDV_GT1, hsw_gt1) CHIPSET(0x0C12, HASWELL_SDV_GT2, hsw_gt2) -CHIPSET(0x0C22, HASWELL_SDV_GT2_PLUS, hsw_gt2) +CHIPSET(0x0C22, HASWELL_SDV_GT3, hsw_gt3) CHIPSET(0x0C06, HASWELL_SDV_M_GT1, hsw_gt1) CHIPSET(0x0C16, HASWELL_SDV_M_GT2, hsw_gt2) -CHIPSET(0x0C26, HASWELL_SDV_M_GT2_PLUS, hsw_gt2) +CHIPSET(0x0C26, HASWELL_SDV_M_GT3, hsw_gt3) CHIPSET(0x0C0A, HASWELL_SDV_S_GT1, hsw_gt1) CHIPSET(0x0C1A, HASWELL_SDV_S_GT2, hsw_gt2) -CHIPSET(0x0C2A, HASWELL_SDV_S_GT2_PLUS, hsw_gt2) +CHIPSET(0x0C2A, HASWELL_SDV_S_GT3, hsw_gt3) CHIPSET(0x0A02, HASWELL_ULT_GT1, hsw_gt1) CHIPSET(0x0A12, HASWELL_ULT_GT2, hsw_gt2) -CHIPSET(0x0A22, HASWELL_ULT_GT2_PLUS, hsw_gt2) +CHIPSET(0x0A22, HASWELL_ULT_GT3, hsw_gt3) CHIPSET(0x0A06, HASWELL_ULT_M_GT1, hsw_gt1) CHIPSET(0x0A16, HASWELL_ULT_M_GT2, hsw_gt2) -CHIPSET(0x0A26, HASWELL_ULT_M_GT2_PLUS, hsw_gt2) +CHIPSET(0x0A26, HASWELL_ULT_M_GT3, hsw_gt3) CHIPSET(0x0A0A, HASWELL_ULT_S_GT1, hsw_gt1) CHIPSET(0x0A1A, HASWELL_ULT_S_GT2, hsw_gt2) -CHIPSET(0x0A2A, HASWELL_ULT_S_GT2_PLUS, hsw_gt2) +CHIPSET(0x0A2A, HASWELL_ULT_S_GT3, hsw_gt3) CHIPSET(0x0D02, HASWELL_CRW_GT1, hsw_gt1) CHIPSET(0x0D12, HASWELL_CRW_GT2, hsw_gt2) -CHIPSET(0x0D22, HASWELL_CRW_GT2_PLUS, hsw_gt2) +CHIPSET(0x0D22, HASWELL_CRW_GT3, hsw_gt3) CHIPSET(0x0D06, HASWELL_CRW_M_GT1, hsw_gt1) CHIPSET(0x0D16, HASWELL_CRW_M_GT2, hsw_gt2) -CHIPSET(0x0D26, HASWELL_CRW_M_GT2_PLUS, hsw_gt2) +CHIPSET(0x0D26, HASWELL_CRW_M_GT3, hsw_gt3) CHIPSET(0x0D0A, HASWELL_CRW_S_GT1, hsw_gt1) CHIPSET(0x0D1A, HASWELL_CRW_S_GT2, hsw_gt2) -CHIPSET(0x0D2A, HASWELL_CRW_S_GT2_PLUS, hsw_gt2) +CHIPSET(0x0D2A, HASWELL_CRW_S_GT3, hsw_gt3) CHIPSET(0x0F31, BAYTRAIL_M_1, byt) CHIPSET(0x0F32, BAYTRAIL_M_2, byt) CHIPSET(0x0F33, BAYTRAIL_M_3, byt) -- cgit v1.2.3