From afa603aedfba85605a6597904e40d4b2032fc069 Mon Sep 17 00:00:00 2001 From: Samuel Iglesias Gonsálvez Date: Thu, 16 Feb 2017 10:47:01 +0100 Subject: i965/fs: fix source type when emitting MOV_INDIRECT to read ICP handles MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When generating the MOV INDIRECT instruction, the source type is ignored and it is set to destination's type. However, this is going to change in a later patch, so we need to explicitly set the proper source type. brw_vec8_grf() creates an float type's fs_reg by default, when the ICP handle is actually unsigned. This patch fixes these cases before applying the aforementioned patch. Signed-off-by: Samuel Iglesias Gonsálvez Cc: "17.0" Reviewed-by: Francisco Jerez (cherry picked from commit d8122128bc6bd291ff0abcb7f2e52d9cdc631527) --- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp index e445e440286..9c46260c729 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp @@ -2005,7 +2005,7 @@ fs_visitor::emit_gs_input_load(const fs_reg &dst, * we might read up to nir->info.gs.vertices_in registers. */ bld.emit(SHADER_OPCODE_MOV_INDIRECT, icp_handle, - fs_reg(brw_vec8_grf(first_icp_handle, 0)), + retype(brw_vec8_grf(first_icp_handle, 0), icp_handle.type), fs_reg(icp_offset_bytes), brw_imm_ud(nir->info.gs.vertices_in * REG_SIZE)); } @@ -2036,7 +2036,7 @@ fs_visitor::emit_gs_input_load(const fs_reg &dst, * we might read up to ceil(nir->info.gs.vertices_in / 8) registers. */ bld.emit(SHADER_OPCODE_MOV_INDIRECT, icp_handle, - fs_reg(brw_vec8_grf(first_icp_handle, 0)), + retype(brw_vec8_grf(first_icp_handle, 0), icp_handle.type), fs_reg(icp_offset_bytes), brw_imm_ud(DIV_ROUND_UP(nir->info.gs.vertices_in, 8) * REG_SIZE)); @@ -2376,7 +2376,7 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder &bld, /* Start at g1. We might read up to 4 registers. */ bld.emit(SHADER_OPCODE_MOV_INDIRECT, icp_handle, - fs_reg(brw_vec8_grf(1, 0)), vertex_offset_bytes, + retype(brw_vec8_grf(1, 0), icp_handle.type), vertex_offset_bytes, brw_imm_ud(4 * REG_SIZE)); } -- cgit v1.2.3