From a5445010e46517708efdcdfd756356bb2193e1bc Mon Sep 17 00:00:00 2001 From: Karol Herbst Date: Sat, 20 Jun 2020 13:50:57 +0200 Subject: gv100/ir: fix atom cas Signed-off-by: Karol Herbst Reviewed-by: Ben Skeggs Part-of: --- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gv100.cpp | 1 + src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gv100.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gv100.cpp index 0fbd47ccf88..9fbea47a8c2 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gv100.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gv100.cpp @@ -858,6 +858,7 @@ CodeEmitterGV100::emitATOM() break; } emitField(73, 3, dType); + emitGPR (64, insn->src(2)); } emitPRED (81); diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp index f100445e9d0..067f9abaca8 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp @@ -1727,7 +1727,8 @@ NVC0LoweringPass::handleCasExch(Instruction *cas, bool needCctl) cctl->setPredicate(cas->cc, cas->getPredicate()); } - if (cas->subOp == NV50_IR_SUBOP_ATOM_CAS) { + if (cas->subOp == NV50_IR_SUBOP_ATOM_CAS && + targ->getChipset() < NVISA_GV100_CHIPSET) { // CAS is crazy. It's 2nd source is a double reg, and the 3rd source // should be set to the high part of the double reg or bad things will // happen elsewhere in the universe. -- cgit v1.2.3