From 8e38947f6c3cabab46660ae64945ad54b2ae0de4 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Mon, 2 Jul 2018 14:17:37 -0700 Subject: i965: Fix BRW_NEW_NUM_SAMPLES to be in .brw, not .mesa This is the wrong kind of dirty bit. Caught by GCC warnings, due to 64-bit values being truncated to 32 bits. Fixes: b95b0e2918c052068caeb4f6c2802ba89be043a3 (intel/anv,blorp,i965: Implement the SKL 16x MSAA SIMD32 workaround) Reviewed-by: Jason Ekstrand --- src/mesa/drivers/dri/i965/genX_state_upload.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c index b279f01e1a1..7fe12887030 100644 --- a/src/mesa/drivers/dri/i965/genX_state_upload.c +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c @@ -4073,13 +4073,13 @@ genX(upload_ps)(struct brw_context *brw) static const struct brw_tracked_state genX(ps_state) = { .dirty = { .mesa = _NEW_MULTISAMPLE | - (GEN_GEN >= 9 ? BRW_NEW_NUM_SAMPLES : 0) | (GEN_GEN < 8 ? _NEW_BUFFERS | _NEW_COLOR : 0), .brw = BRW_NEW_BATCH | BRW_NEW_BLORP | - BRW_NEW_FS_PROG_DATA, + BRW_NEW_FS_PROG_DATA | + (GEN_GEN >= 9 ? BRW_NEW_NUM_SAMPLES : 0), }, .emit = genX(upload_ps), }; -- cgit v1.2.3