From 3e99271163f1e07758d43bddb9ff1be6576a186b Mon Sep 17 00:00:00 2001 From: Ilia Mirkin Date: Thu, 25 Feb 2021 23:08:00 -0500 Subject: nv50/ir: force shared memory indirect to be an address The upstream logic will not end up using an address, so we have to force it here. The other backends don't care either. Signed-off-by: Ilia Mirkin Reviewed-by: Pierre Moreau Part-of: --- .../nouveau/codegen/nv50_ir_lowering_nv50.cpp | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp index e03af380bbf..b9d71de2e48 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp @@ -626,6 +626,7 @@ private: bool handlePFETCH(Instruction *); bool handleEXPORT(Instruction *); bool handleLOAD(Instruction *); + bool handleLDST(Instruction *); bool handleDIV(Instruction *); bool handleSQRT(Instruction *); @@ -1294,6 +1295,13 @@ bool NV50LoweringPreSSA::handleLOAD(Instruction *i) { ValueRef src = i->src(0); + Symbol *sym = i->getSrc(0)->asSym(); + + if (prog->getType() == Program::TYPE_COMPUTE) { + if (sym->inFile(FILE_MEMORY_SHARED)) { + return handleLDST(i); + } + } if (src.isIndirect(1)) { assert(prog->getType() == Program::TYPE_GEOMETRY); @@ -1330,6 +1338,32 @@ NV50LoweringPreSSA::handleLOAD(Instruction *i) return true; } +bool +NV50LoweringPreSSA::handleLDST(Instruction *i) +{ + ValueRef src = i->src(0); + Symbol *sym = i->getSrc(0)->asSym(); + + if (prog->getType() != Program::TYPE_COMPUTE || + !sym->inFile(FILE_MEMORY_SHARED)) { + return true; + } + + if (src.isIndirect(0)) { + Value *addr = i->getIndirect(0, 0); + + if (!addr->inFile(FILE_ADDRESS)) { + // Move address from GPR into an address register + Value *new_addr = bld.getSSA(2, FILE_ADDRESS); + bld.mkMov(new_addr, addr); + + i->setIndirect(0, 0, new_addr); + } + } + + return true; +} + bool NV50LoweringPreSSA::handlePFETCH(Instruction *i) { @@ -1427,6 +1461,8 @@ NV50LoweringPreSSA::visit(Instruction *i) return handleEXPORT(i); case OP_LOAD: return handleLOAD(i); + case OP_STORE: + return handleLDST(i); case OP_RDSV: return handleRDSV(i); case OP_WRSV: -- cgit v1.2.3