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2018-12-14freedreno/a6xx: fix corrupted uniformsRob Clark1-1/+2
2018-12-14i965/gen9: Add workarounds for object preemption.Rafael Antognolli1-0/+63
2018-12-14i965/gen10+: Enable object level preemption.Rafael Antognolli4-1/+36
2018-12-14intel/genxml: Add register for object preemption.Rafael Antognolli3-0/+24
2018-12-14util/slab: Rename slab_mempool typed parameters to mempoolIan Romanick2-14/+14
2018-12-14nir/phi_builder: Internal users should use nir_phi_builder_value_set_block_de...Ian Romanick1-2/+2
2018-12-14etnaviv: drop redundant ctx function parameterChristian Gmeiner1-4/+3
2018-12-14genxml: Consistently use a numeric "MOCS" fieldKenneth Graunke16-260/+177
2018-12-14nir: fix opt_if_loop_last_continue()Timothy Arceri1-2/+6
2018-12-13freedreno/a6xx: fix resource_copy_region()Rob Clark1-9/+24
2018-12-13freedreno: move fd_resource_copy_region()Rob Clark3-62/+73
2018-12-13freedreno/a6xx: more blitter fixesRob Clark1-10/+22
2018-12-13freedreno: update generated headersRob Clark8-30/+39
2018-12-13gallium/aux: add is_unorm() helperRob Clark2-0/+24
2018-12-13freedreno/a6xx: fix blitter crashRob Clark1-0/+17
2018-12-13freedreno/ir3: don't remove unused input componentsRob Clark1-1/+7
2018-12-13freedreno/ir3: fix crashRob Clark1-14/+8
2018-12-13freedreno: also set DUMP flag on shadersRob Clark5-20/+22
2018-12-13freedreno: debug GEM obj namesRob Clark13-21/+91
2018-12-13freedreno/drm: sync uapi and enable softpinRob Clark6-25/+30
2018-12-13nir: Move intel's half-float image store lowering to to nir_format.h.Eric Anholt2-8/+15
2018-12-13Revert "intel: Simplify the half-float packing in image load/store lowering."Eric Anholt1-2/+8
2018-12-13nir: Print the format of image variables.Eric Anholt1-0/+47
2018-12-13mesa/st: Expose compute shaders when NIR support is advertised.Eric Anholt2-8/+14
2018-12-13radv/xfb: fix counter buffer bounds checks.Dave Airlie1-2/+2
2018-12-13i965: Enable nir_opt_idiv_const for 32 and 64-bit integersJason Ekstrand1-1/+3
2018-12-13i965/vec4: Implement nir_op_uadd_satJason Ekstrand1-0/+6
2018-12-13i965/fs: Implement nir_op_uadd_satIan Romanick1-0/+5
2018-12-13nir: Add a pass for lowering integer division by constantsJason Ekstrand4-0/+219
2018-12-13nir: Add a saturated unsigned integer add opcodeIan Romanick1-0/+2
2018-12-13nir/lower_int64: Add support for [iu]mul_highJason Ekstrand2-0/+67
2018-12-13nir: Allow [iu]mul_high on non-32-bit typesJason Ekstrand2-4/+40
2018-12-13glx: mandate xf86vidmode only for "drm" dri platformsEmil Velikov1-2/+4
2018-12-13nir: remove unused variableAlejandro Piñeiro1-1/+0
2018-12-13virgl: work around bad assumptions in virglrendererErik Faye-Lund1-1/+32
2018-12-13virgl: wrap vertex element state in a structErik Faye-Lund2-9/+21
2018-12-13virgl: simplify virgl_hw_set_index_bufferErik Faye-Lund1-3/+2
2018-12-13virgl: simplify virgl_hw_set_vertex_buffersErik Faye-Lund1-4/+2
2018-12-13radv: don't check if format is depth in radv_image_can_enable_hile()Samuel Pitoiset1-1/+0
2018-12-13radv: check if addrlib enabled HTILE in radv_image_can_enable_htile()Samuel Pitoiset1-1/+2
2018-12-13radv: switch on EOP when primitive restart is enabled with triangle stripsSamuel Pitoiset1-2/+1
2018-12-13radv: allow to skip DCC decompressions with the new predicateSamuel Pitoiset1-6/+13
2018-12-13radv: add a predicate for reflecting DCC decompression stateSamuel Pitoiset5-1/+44
2018-12-12i965/compute: Emit GPGPU_WALKER in genX_state_uploadJordan Justen3-130/+105
2018-12-12i965/genX_state: Add register access functionsJordan Justen1-0/+31
2018-12-12intel: Simplify the half-float packing in image load/store lowering.Eric Anholt1-8/+2
2018-12-12nir: Pull some of intel's image load/store format conversion to nir_format.hEric Anholt2-18/+40
2018-12-12nir: Add some more consts to the nir_format_convert.h helpers.Eric Anholt1-7/+6
2018-12-13nir: detect more induction variablesTimothy Arceri1-0/+36
2018-12-13nir: reword code commentTimothy Arceri1-2/+2
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