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2019-01-13i965: Drop mark_surface_used mechanism.Kenneth Graunke10-105/+7
The original idea was that the backend compiler could eliminate surfaces, so we would have it mark which ones are actually used, then shrink the binding table accordingly. Unfortunately, it's a pretty blunt mechanism - it can only prune things from the end, not the middle - since we decide the layout before we even start the backend compiler, and only limit the size. It also basically gives up if it sees indirect array access. Besides, we do the vast majority of our surface elimination in NIR anyway, not the backend - and I don't see that trend changing any time soon. Vulkan abandoned this plan a long time ago, and I don't use it in Iris, but it's still been kicking around in i965. I hacked shader-db to print the binding table size in bytes, and observed no changes with this patch. So, this code appears to do nothing useful. Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2019-01-13egl: fix python lib deprecation warningEric Engestrom3-14/+7
DeprecationWarning: the imp module is deprecated in favour of importlib Instead of complicated logic, just import the file directly. Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2019-01-12spirv: Emit switch conditions on-the-flyJason Ekstrand1-36/+26
Instead of emitting all of the conditions for the cases of a switch statement up-front, emit them on-the-fly as we emit the code for each case. The original justification for this was that we were going to have to build a default case anyway which would need them all. However, we can just trust CSE to clean up the mess in that case. Emitting each condition right before the if statement that uses it reduces register pressure and, in one customer benchmark, reduces spilling and improves performance by about 2x. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-01-12nir/gcm: Support deref instructionsJason Ekstrand1-0/+4
Even though no one's been brave enough to ever use this pass, I like to keep it functionally working. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-01-12intel/nir: Call nir_opt_deref in brw_nir_optimizeJason Ekstrand1-0/+1
It's an optimization so we should probably be calling it in the optimization loop. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-01-12spirv: Contain the GLSLang issue #179 workaround to old GLSLangJason Ekstrand3-18/+38
Instead of applying the workaround universally, detect semi-old GLSLang via the generator ID and only enable the workaround on old GLSLang. This isn't nearly as precise as one would like it to be because the first GLSLang generator id version bump was on October 7, 2017 which is about 1.5 years after the bug was fixed. However, it at least lets us disable it for non-GLSLang and for more modern versions. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-01-12spirv: Whack sampler/image pointers to uniformJason Ekstrand1-0/+12
A long time in a galaxy far far away, there was a GLSLang bug with how it handled samplers passed in as function parameters. (The bug can be found here: https://github.com/KhronosGroup/glslang/issues/179.) Unfortunately, that version was shipped in several apps and has been causing heartburn for our SPIR-V parser ever since. Recent changes to NIR uncovered a moderately old bug in how we work around this issue. In particular, we ended up with a deref_cast from uniform to local which is not a no-op cast so nir_opt_deref wasn't getting rid of the cast. The only reason why it worked before was because someone just happened to call nir_fixup_deref_modes which "fixed" the cast (that shouldn't be happening) and then a later round of copy-prop would get rid of it. The fact that the deref_cast survived that long without causing trouble for other parts of NIR is a bit surprising. Just whacking the mode of the pointer seems to fix it fairly unobtrusively. Currently, only apps with this bug will have a local variable containing an image or sampler. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109304 Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-01-11st/nir: Lower TES gl_PatchVerticesIn to a constant if linked with a TCS.Kenneth Graunke1-0/+23
If the TCS and TES are linked together, we can simply replace the TES's gl_PatchVerticesIn system value with a constant, possibly allowing extra optimization or letting the driver avoid uploading a special value. Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-01-11glsl/nir: keep bool types when native_integers=falseJonathan Marek1-98/+63
With the new handling of bool types, the conversion to float in glsl_to_nir should not apply to bool types anymore. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-01-11glsl/nir: ftrunc for native_integers=false float to int castJonathan Marek1-0/+4
out_type in the default cast case is always GLSL_TYPE_FLOAT, so we get a mov otherwise. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-01-11glsl/nir: int constants as float for native_integers=falseJonathan Marek1-4/+12
All alu instructions emitted with native_integers=false expect float (or bool in some cases) constants, so this change is necessary. This will cause changes with some intrinsics which had integer sources, such as nir_intrinsic_load_uniform. Apparently it might cause issues with some opt passes, but perhaps those don't apply in OpenGL ES 2.0 cases? Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-01-11intel/peephole_ffma: Fix swizzle propagationJason Ekstrand1-4/+7
The num_components value passed into get_mul_for_src is used to only compose the parts of the swizzle that we know will be used so we don't compose invalid swizzle components. However, we had a bug where we passed the number of components of the add all the way through. For the given source, we need the number of components read from that source. In the case where we have a narrow add, say 2 components, that is sourced from a chain of wider instructions, we may not compose all the swizzles. All we really need to do is pass through the right number of components at each level. Fixes: 2231cf0ba3a "nir: Fix output swizzle in get_mul_for_src" Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2019-01-11nir: Allow a non-existent sampler deref in nir_lower_samplers_as_derefKenneth Graunke1-19/+21
GL_ARB_gl_spirv does not provide a sampler deref for e.g. texelFetch(), so we can't assume that both are present and identical. Simply lower each if it is present. Fixes regressions in GL_ARB_gl_spirv tests since I switched everyone to using this pass. Thanks to Alejandro Piñeiro for catching these. Fixes: f003859f97c nir: Make gl_nir_lower_samplers use gl_nir_lower_samplers_as_deref Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Tested-by: Alejandro Piñeiro <apinheiro@igalia.com>
2019-01-11egl: remove unused includeEric Engestrom1-2/+0
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Acked-by: Emil Velikov <emil.velikov@collabora.com>
2019-01-11egl: add missing includesEric Engestrom6-0/+9
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Acked-by: Emil Velikov <emil.velikov@collabora.com>
2019-01-11anv/pipeline_cache: fix incorrect guards for NIR cacheIago Toral Quiroga1-2/+3
Fixes: f6aa9f718516 'anv/pipeline_cache: Add support for caching NIR' Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-01-10blorp: Pass the batch to lookup/upload_shader instead of contextKenneth Graunke7-35/+44
This will allow drivers to pin shader buffers if necessary. i965 and anv do not need to do this today, but iris will. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-01-10blorp: Add blorp_get_surface_address to the driver interface.Kenneth Graunke3-0/+27
Currently, BLORP expects drivers to provide two functions for dealing with buffers: blorp_emit_reloc and blorp_surface_reloc. Both record a relocation and combine the BO address and offset into a full 64-bit address. Traditionally, blorp_surface_reloc has written that combined address to an implicitly-known buffer where surface states are stored. (In contrast, blorp_emit_reloc returns the value.) The upcoming Iris driver stores surface states in multiple buffers, which makes it impossible for blorp_surface_reloc to write the combined address - it only takes an offset, not the actual buffer to write to. This commit adds a third function, blorp_get_surface_address, which combines and returns an address, which is then passed to ISL's surface state fill functions. Softpin-only drivers can return a real address here and skip writing it in blorp_surface_reloc. Relocation-based drivers are have options. They can simply return 0 from the new function, and continue writing the address from blorp_surface_reloc. Or, they can return a presumed address from blorp_get_surface_address, and have other relocation processing write the real value later. For now, i965 and anv simply return 0. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-01-10docs: fix gallium screen cap docsIlia Mirkin1-11/+11
Make sure that the next line starts with spaces so that bullets are maintained throughout, add `` around a few more special tokens, and fix SAMPLE_COUNT_TEXTURE -> SAMPLE_COUNT. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Dave Airlie <airlied@redhat.com>
2019-01-11glsl: Make invariant outputs in ES fragment shader not to cause errorDanylo Piliaiev1-1/+1
In all GLSL ES versions output variables in fragment shader are allowed to be invariant. From Section 4.6.1 ("The Invariant Qualifier") GLSL ES 1.00 spec: "Only the following variables may be declared as invariant: ... - Built-in special variables output from the fragment shader." From Section 4.6.1 ("The Invariant Qualifier") GLSL ES 3.00 spec: "Only variables output from a shader can be candidates for invariance." Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107842
2019-01-10anv/pipeline: Cache the pre-lowered NIRJason Ekstrand1-10/+39
This adds a second level of caching for the pre-lowered NIR that's only based off of the shader module, entrypoint and specialization constants. This is enough for spirv_to_nir as well as our first round of lowering and optimization. Caching at this level should allow for faster shader recompiles due to state changes. The NIR caching does not get serialized to disk via either the VkPipelineCache serialization mechanism or the transparent on-disk cache. We could but it's usually not that expensive to fall back to SPIR-V for the odd cache miss especially if it only happens once for several misses and it simplifies the cache. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-01-10anv/pipeline_cache: Add support for caching NIRJason Ekstrand2-0/+118
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-01-10anv/pipeline: Hash shader modules and spec constants separatelyJason Ekstrand1-15/+39
The stuff hashed by anv_pipeline_hash_shader is exactly the inputs to anv_shader_compile_to_nir so it can be used for NIR caching. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-01-10compiler/types: Serialize/deserialize subpass input types correctlyJason Ekstrand1-2/+2
They have glsl_sampler_dim enum values of 8 and 9 which don't work when you & them with 0x7. Fortunately, we have plenty of bits. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-01-10anv/pipeline: Move wpos and input attachment lowering to lower_nirJason Ekstrand1-11/+8
This lets us make anv_pipeline_compile_to_nir take a device instead of a pipeline. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-01-10i965: Compile fp64 funcs only if we do not have 64-bit hardware supportMatt Turner1-1/+1
Brown bag fix...
2019-01-10anv/pipeline: Constant fold after apply_pipeline_layoutJason Ekstrand2-12/+5
Thanks to the new NIR load_descriptor intrinsic added by the UBO/SSBO lowering series, we weren't getting UBO pushing because the UBO range detection pass couldn't see the constants it needed. This fixes that problem with a quick round of constant folding. Because we're folding we no longer need to go out of our way to generate constants when we lower the vulkan_resource_index intrinsic and we can make it a bit simpler. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-01-10freedreno/a6xx: fix 3d+tiled layoutRob Clark1-34/+52
The last round of fixing 3d layer+level layout skipped the tiled case, since tiled texture support was not in place yet. This finishes the job. Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-01-10freedreno/a6xx: move tile_mode to sampler-view CSORob Clark2-7/+7
This is known when the CSO is created, so no need to patch it in later. Also, it seems like smaller textures where the first level is small enough to be linear, it seems like we should set linear tile mode. See: dEQP-GLES3.functional.texture.format.unsized.rgb_unsigned_byte_3d_pot Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-01-10freedreno/a6xx: separate stencil restore/resolve fixesRob Clark1-14/+21
Previously we'd use format/etc from the primary (z32) buffer for the stencil (s8), due to confusion about rsc vs psurf. Rework this to drop extra arg and push down handling of separate stencil case (and make sure we take the fmt from the right place). This doesn't completely fix separate-stencil, but at least it avoids the GPU scribbling over random other cmdstream buffers and causing a bunch of bogus fails in dEQP. Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-01-10freedreno: make cmdstream bo's read-only to GPURob Clark2-5/+11
If nothing else, this will make problems with cmdstream getting blit over with pixels easier to track down (ie. faults when it first happens rather than strange failures later from corrupted cmdstream when a stateobj is later reused). (NOTE this somewhat depends on the kernel supporting the flag, and the iommu implementation. But the worst case is just that the cmdstream ends up writeable as before.) Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-01-10etnaviv: fix typo in cflush_all descriptionGuido Günther1-1/+1
Signed-off-by: Guido Günther <guido.gunther@puri.sm> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-01-10radv: remove a few more unnecessary KHR suffixesEric Engestrom3-11/+11
Cc: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (v1)
2019-01-10nir: fix copy-paste error in nir_lower_constant_initializersRhys Perry1-2/+2
Fixes: 393b59e0772e7bf0426bdf61c740752c4e09dde1 ('nir: Rework nir_lower_constant_initializers() to handle functions') Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-01-10glsl/linker: specify proper direction in location aliasing errorAndres Gomez1-5/+10
The check for location aliasing was always asuming output variables but this validation is also called for input variables. Fixes: e2abb75b0e4 ("glsl/linker: validate explicit locations for SSO programs") Cc: Iago Toral Quiroga <itoral@igalia.com> Signed-off-by: Andres Gomez <agomez@igalia.com> Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2019-01-10intel/isl: move tiled_memcpy static libs from i965 to islTapani Pälli21-401/+381
Patch moves intel_tiled_memcpy[_sse41] libraries to isl, renames some functions and types and makes the required build system changes for meson, automake and Android. No functional changes are introduced. v2: code cleanups, move isl_get_memcpy_type to i965 (Jason) v3: move isl_mem_copy_fn to priv header, cleanups (Jason, Dylan) Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Dylan Baker <dylan@pnwbakers.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2019-01-09i965: Enable 64-bit GLSL extensionsMatt Turner1-4/+4
Now that we have software implementations of ARB_gpu_shader_int64 and ARB_gpu_shader_fp64 we can unconditionally enable these extensions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-01-09i965: Compile fp64 software routines and lower double-opsMatt Turner4-23/+133
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-01-09intel/compiler: Heap-allocate temporary storageMatt Turner1-3/+5
Shaders containing software implementations of double-precision operations can be very large such that we cannot stack-allocate an array of grf_count*16. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-01-09intel/compiler: Expand size of the 'nr' fieldMatt Turner1-4/+3
Shaders containing software implementations of double-precision operations can be very large such that we have more the 2^16 virtual registers during optimization. Move the 'nr' field to the union containing the immediate storage and expand it to 32-bits. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-01-09intel/compiler: Prevent warnings in the following patchMatt Turner11-36/+38
The next patch replaces an unsigned bitfield with a plain unsigned, which triggers gcc to begin warning on signed/unsigned comparisons. Keeping this patch separate from the actual move allows bisectablity and generates no additional warnings temporarily. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-01-09intel/compiler: Rearrange code to avoid future problemsMatt Turner1-3/+4
A follow on commit will move nr to the same union as the immediate data, so we should assert these invariants before we overwrite the nr field. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-01-09intel/compiler: Avoid false positive assertionsMatt Turner1-6/+6
A follow on patch will move the 'nr' field to the union containing the immediate field, so prepare by checking that we're only testing these assertions if the .file is correct. The assertions with != ARF were kind of silly to begin with because the <128 check is specifically only for things in the GRF. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-01-09intel/compiler: Split 64-bit MOV-indirects if neededMatt Turner1-1/+2
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-01-09intel/compiler: Lower 64-bit MOV/SEL operationsMatt Turner1-1/+49
2019-01-09nir: Unset metadata debug bit if no progress madeMatt Turner22-12/+115
NIR metadata validation verifies that the debug bit was unset (by a call to nir_metadata_preserve) if a NIR optimization pass made progress on the shader. With the expectation that the NIR shader consists of only a single main function, it has been safe to call nir_metadata_preserve() iff progress was made. However, most optimization passes calculate progress per-function and then return the union of those calculations. In the case that an optimization pass makes progress only on a subset of the functions in the shader metadata validation will detect the debug bit is still set on any unchanged functions resulting in a failed assertion. This patch offers a quick solution (short of a larger scale refactoring which I do not wish to undertake as part of this series) that simply unsets the debug bit on unchanged functions. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-01-09nir: Add lowering support for 64-bit operations to softwareMatt Turner2-2/+178
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-01-09nir: Create nir_builder in nir_lower_doubles_impl()Matt Turner1-17/+19
We're going to use it more in a future patch, and this avoids a lot of gross code. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-01-09nir: Add and set info::uses_64bitMatt Turner2-0/+10
Will be used to communicate that a shader uses 64-bit operations to the concerned lowering passes. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-01-09nir: Implement lowering of 64-bit shift operationsMatt Turner2-0/+143
Reviewed-by: Elie Tournier <tournier.elie@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>