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path: root/src/panfrost/bifrost/ISA.xml
AgeCommit message (Expand)AuthorFilesLines
2023-01-02pan/bi: Rename panfrost/bifrost -> panfrost/compilerAlyssa Rosenzweig1-9317/+0
2022-09-02pan/bi: Add phi nodesAlyssa Rosenzweig1-0/+2
2022-09-02pan/bi: Don't write registers in optimizer testsAlyssa Rosenzweig1-1/+1
2022-09-02pan/bi: Use variable src/dest for collect/splitAlyssa Rosenzweig1-2/+2
2022-09-02pan/bi: Introduce TEXC_DUAL psuedoinstructionAlyssa Rosenzweig1-1/+17
2022-09-02pan/bi: Model 3rd source for ATESTAlyssa Rosenzweig1-0/+3
2022-09-02pan/bi: Model [IF]CMP_{OR,AND,MULTI} opsAlyssa Rosenzweig1-0/+452
2022-08-01pan/bi: Rename CLPER_V6.i32 to CLPER_OLD.i32Alyssa Rosenzweig1-1/+1
2022-06-21pan/bi: Model MKVEC.v2i8Alyssa Rosenzweig1-0/+18
2022-06-21pan/bi: Remove FRSCALE from IRAlyssa Rosenzweig1-30/+0
2022-06-21pan/bi: Fix LD_BUFFER.i16 definitionAlyssa Rosenzweig1-1/+1
2022-05-30pan/bi: Model Valhall source formatsAlyssa Rosenzweig1-0/+24
2022-05-30pan/bi: Make LD_VAR w=format instead of w=vecsizeAlyssa Rosenzweig1-1/+1
2022-05-19pan/bi: Add collect and split instructionsAlyssa Rosenzweig1-0/+6
2022-04-25pan/bi: Implement fquantize2f16Alyssa Rosenzweig1-0/+3
2022-04-07pan/bi: Mark LD_TILE as w=formatAlyssa Rosenzweig1-1/+1
2022-04-07pan/bi: Model Valhall image loadsAlyssa Rosenzweig1-0/+46
2022-03-30pan/bi: Fix write_mask sizeAlyssa Rosenzweig1-3/+3
2022-03-30pan/bi: Add .shadow modifier to TEX_GATHERAlyssa Rosenzweig1-0/+1
2022-03-25pan/bi: Model LD_VAR_BUF instructionsAlyssa Rosenzweig1-0/+60
2022-03-25pan/bi: Augment ST_TILE with register formatAlyssa Rosenzweig1-0/+6
2022-03-25pan/bi: Model Valhall-style A(CMP)XCHGAlyssa Rosenzweig1-0/+2
2022-03-25pan/bi: Add ATOM_RETURN pseudo-instructionAlyssa Rosenzweig1-0/+24
2022-03-25pan/bi: Rename PATOM_C to ATOMAlyssa Rosenzweig1-4/+4
2022-03-03pan/bi: Add arithmetic flag to RSHIFT opsAlyssa Rosenzweig1-0/+9
2022-03-03pan/bi: Extend LD_TILE with a register formatAlyssa Rosenzweig1-0/+6
2022-03-03pan/bi: Add BRANCHZI instructionAlyssa Rosenzweig1-0/+9
2022-03-03pan/bi: Model LD_BUFFER instructionsAlyssa Rosenzweig1-0/+72
2022-03-03pan/bi: Model offset for LOAD/STOREAlyssa Rosenzweig1-0/+16
2022-03-03pan/bi: Model pos/vary segments in STORE instructionsAlyssa Rosenzweig1-16/+16
2022-03-03pan/bi: Model LEA_BUF_IMM in the IRAlyssa Rosenzweig1-0/+4
2022-03-03pan/bi: Add LD_VAR_BUF_IMM.f16/f32 instructionsAlyssa Rosenzweig1-0/+60
2022-03-03pan/bi: Extend BLEND to take a register formatAlyssa Rosenzweig1-0/+11
2022-03-03pan/bi: Model Valhall texture instructionsAlyssa Rosenzweig1-0/+147
2022-03-01pan/bi: Add BI_SUBGROUP_SUBGROUP16 optionAlyssa Rosenzweig1-0/+1
2022-03-01pan/bi: Mark NOP as having no destinationsAlyssa Rosenzweig1-2/+2
2022-01-02pan/bi: Use fused dual source blendingAlyssa Rosenzweig1-0/+3
2021-11-12pan/bi: Add second destination to TEXCAlyssa Rosenzweig1-1/+2
2021-08-20pan/bi: Correct the sr_count on +ST_TILEAlyssa Rosenzweig1-1/+1
2021-08-11pan/bi: Fuse DISCARD with conditionsAlyssa Rosenzweig1-0/+9
2021-08-11pan/bi: Use FCLAMP pseudo op for clamp propAlyssa Rosenzweig1-0/+20
2021-08-11pan/bi: Use FABSNEG pseudo ops for modifier propAlyssa Rosenzweig1-0/+23
2021-07-28pan/bi: Rename CLPER_V7 back to CLPERAlyssa Rosenzweig1-1/+1
2021-07-28pan/bi: Rename NOP.i32 to NOPAlyssa Rosenzweig1-2/+2
2021-07-28pan/bi: Model RSCALE for ValhallAlyssa Rosenzweig1-0/+30
2021-07-28pan/bi: Model *ADD_IMM instructions in IRAlyssa Rosenzweig1-0/+25
2021-07-09pan/bi: Track LOD mode even for TEXCAlyssa Rosenzweig1-0/+4
2021-05-03pan/bi: Replace lane0 modifier with lane_dest for load instructionsIcecream951-25/+25
2021-05-03pan/bi: Add missing sr_count to pseudo-atomicsAlyssa Rosenzweig1-0/+4
2021-04-03pan/bi: Handle 16-bit blend sr_countAlyssa Rosenzweig1-1/+3
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