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path: root/src/mesa/drivers/dri/i965/intel_tex.c
AgeCommit message (Expand)AuthorFilesLines
2017-10-12meta: Delete the PBO texture upload/download pathJason Ekstrand1-63/+0
2017-08-30i965: drop brw->gen in favor of devinfo->genLionel Landwerlin1-1/+2
2017-08-19i965/tex: Don't pass samples to miptree_create_for_teximageJason Ekstrand1-1/+1
2017-08-07i965/miptree: Rework create flagsJason Ekstrand1-2/+2
2017-08-07i965/miptree: Delete MIPTREE_LAYOUT_TILING_(Y|ANY)Jason Ekstrand1-1/+1
2017-07-22i965/miptree: Check tex image allocation failuresTopi Pohjolainen1-0/+2
2017-07-20i965/miptree: Use num_samples of 1 instead of 0 for single-sampledTopi Pohjolainen1-2/+2
2017-07-13i965: Add a "write" parameter to intel_bufferobj_buffer.Kenneth Graunke1-1/+2
2017-06-22i965: Rename some vague format members of brw_contextChad Versace1-1/+1
2017-04-10i965/drm: Rename drm_bacon_bo to brw_bo.Kenneth Graunke1-1/+1
2017-04-10i965/drm: Use our internal libdrm (drm_bacon) rather than the real one.Kenneth Graunke1-1/+1
2016-09-20i965: Rename intelScreen to screen.Kenneth Graunke1-2/+2
2016-08-19i965: Roll intel_reg.h into brw_defines.hJason Ekstrand1-1/+1
2016-07-20i965/miptree: Enforce that height == 1 for 1-D array texturesJason Ekstrand1-0/+2
2016-07-07i965: Emit SNB write cache flush W/A from brw_emit_pipe_control_flush.Francisco Jerez1-8/+0
2016-07-01i965: intel_texture_barrier reimplementedAlejandro Piñeiro1-1/+20
2015-09-23i965: add ARB_texture_barrier supportIlia Mirkin1-0/+9
2015-08-06i965: Rename MIPTREE_LAYOUT_ALLOC_* -> MIPTREE_LAYOUT_TILING_*.Matt Turner1-1/+1
2015-07-16i965: Push miptree tiling request into flagsBen Widawsky1-1/+1
2015-07-16Revert "i965: Push miptree tiling request into flags"Ben Widawsky1-1/+1
2015-07-16i965: Push miptree tiling request into flagsBen Widawsky1-1/+1
2015-06-12i965: Consolidate certain miptree params to flagsBen Widawsky1-5/+3
2015-04-14i965: replace __FUNCTION__ with __func__Marius Predut1-5/+5
2015-04-13i965: Change intel_miptree_create_for_bo() signatureChad Versace1-1/+2
2015-01-28i965/tex: Don't create read-write textures with non-renderable formatsJason Ekstrand1-0/+5
2015-01-22i965: Implement SetTextureStorageForBufferObjectJason Ekstrand1-0/+57
2015-01-08main: Changed _mesa_alloc_texture_storage to _mesa_AllocTextureStorage_sw.Laura Ekstrand1-1/+1
2014-12-22i965: Fix intel_miptree_map() signature to be more 64-bit safeChad Versace1-2/+5
2014-08-15i965: Allow forcing miptree->array_layout = ALL_SLICES_AT_EACH_LODJordan Justen1-1/+2
2014-06-26i965: Handle miptree creation failure in intel_alloc_texture_storage()Juha-Pekka Heikkila1-0/+3
2014-04-10i965: Adjust map/unmap code for MinLevel/MinLayerChris Forbes1-3/+8
2014-04-10i965: Add _Format to intel_texobj.Chris Forbes1-0/+9
2014-04-10i965: Add driver hook for TextureViewChris Forbes1-0/+41
2013-12-05i965: Drop trailing whitespace from the rest of the driver.Kenneth Graunke1-1/+1
2013-09-30i965: Add a real native TexStorage path.Eric Anholt1-0/+63
2013-07-30mesa: default DEPTH_TEXTURE_MODE should be RED in the core profileMarek Olšák1-1/+1
2013-07-09i965: Move intel_context::intelScreen to brw_context.Kenneth Graunke1-2/+1
2013-07-09i965: Pass brw_context to functions rather than intel_context.Kenneth Graunke1-5/+6
2013-07-09i965: Replace #include "intel_context.h" with brw_context.h.Kenneth Graunke1-1/+1
2013-06-26i965: Move the remaining intel code to the i965 directory.Eric Anholt1-1/+189
2007-12-16[965] Move to using shared texture management code.Eric Anholt1-316/+1
2007-11-20[965] Replace 965 texture format code with common code.Eric Anholt1-0/+1
2006-08-09Add Intel i965G/Q DRI driver.Eric Anholt1-0/+315