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2021-03-11i965: Rename files with "intel_" prefix to "brw_"Anuj Phogat1-3295/+0
v2: Rename intel_batchbuffer.c to intel_batch.c and intel_batchbuffer.h to intel_batch.h Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9510>
2021-02-25i965: Eliminate all tabs except in brw_defines.hKenneth Graunke1-61/+61
For a while we were doing 3-space indent with 8-space tabs, largely due to the emacs settings of a couple of contributors. We stopped using tabs a long time ago, and they're just a nuisance at this point. Acked-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9207>
2021-02-25i965: Rename some camel-case local variablesKenneth Graunke1-12/+12
Acked-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9207>
2021-02-25i965: Rename the rest of intel_* functions to brw_*Kenneth Graunke1-26/+26
Acked-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9207>
2021-02-25i965: Rename intel_image_format and intel_buffer to brw_*Kenneth Graunke1-1/+1
Acked-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9207>
2021-02-25i965: Rename intel_mip* to brw_mip*.Kenneth Graunke1-492/+485
With lots of indentation fixes. Acked-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9207>
2021-02-25i965: Rename intel_renderbuffer to brw_renderbufferKenneth Graunke1-2/+2
For now, keeping the 'irb' name on local variables. Acked-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9207>
2021-02-25i965: Rename intel_texture_{object,image} to brw_texture_{object,image}Kenneth Graunke1-4/+4
Acked-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9207>
2021-02-25i965: Rename intel_batchbuffer_* to brw_batch_*.Kenneth Graunke1-1/+1
Shorter, matching the convention in iris, and drops use of "intel_" on i965-specific code that isn't shared. Acked-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9207>
2021-02-25i965: Rename use_intel_mipree_map_blit to use_blitter_to_mapKenneth Graunke1-4/+4
Mip...ree? Use a more descriptive name instead of just fixing the typo. Acked-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9207>
2021-02-10i965,iris: Delete misleading HiZ sampling commentsNanley Chery1-8/+1
One comment seems to suggest that MCS (which is needed for compressed multisampling) can be used to sample from a multisampled depth buffer. This is not the case. Multisampled depth buffers are sampled without an auxiliary surface. Another comment seems to suggest that some depth buffers don't have corresponding levels in their HiZ buffers. Each main slice *should* have a corresponding aux slice, but not all of these slices have equal support for HiZ ops (e.g. ambiguates aren't really supported on non-8x4-aligned slices). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8853>
2020-12-30intel/isl: move get_tile dims/masks to common isl headerDave Airlie1-47/+1
Both classic and iris have the same code for this, but none of it is dependent on drivers, so just add inline helpers to isl. Acked-by: Tapani Pälli <tapani.palli@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8253>
2020-10-15i965: Remove Gen10-specific state setup and workaroundsIan Romanick1-23/+4
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6899>
2020-10-06i965: drop likely/unlikely around INTEL_DEBUGMarcin Ślusarz1-1/+1
It's included in declaration of INTEL_DEBUG. Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com> Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6732>
2020-04-21replace imports memory functions with utils memory functionsDylan Baker1-4/+5
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> Reviewed-by: Matt Turner <mattst88@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3024>
2020-02-24i965: Use isl_aux_state_transition_write()Nanley Chery1-183/+16
v2. Dirty shadow miptrees independent of aux. (Jason) Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2957> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2957>
2020-02-24i965: Use ISL's access preparation functionsNanley Chery1-257/+35
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2957>
2019-10-28intel: Support HIZ_CCS in isl_surf_get_ccs_surfNanley Chery1-4/+4
Add an extra aux parameter which will be filled out with CCS if the first two isl_surf parameters fit the requirements for HiZ_CCS. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-28i965/miptree: Avoid -Wswitch for the Gen12 aux modesNanley Chery1-0/+3
Avoid the compiler warnings for the new enums that will be introduced in a future commit. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2019-10-20mesa: Redefine the RG formats as array formats.Eric Anholt1-2/+2
This is the layout used in the GL API, and maps directly to PIPE formats with no endianness trickery. As with the LA change, this fixes big-endian fetching from texbos. Also cleans up some endian shenanigans in shader images. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-07-31intel: drop incorrect MAYBE_UNUSEDEric Engestrom1-2/+2
All these are actually always used. Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2019-05-14i965/miptree: Refactor intel_miptree_supports_ccs_e()Nanley Chery1-10/+5
Update and rename this function to format_supports_ccs_e() to better match its behavior. Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2019-05-14i965/miptree: Drop intel_*_supports_hiz()Nanley Chery1-35/+2
intel_tiling_supports_hiz() and intel_miptree_supports_hiz() duplicate much the work done by isl_surf_get_hiz_surf(). Replace them with simple expressions. Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2019-05-14i965/miptree: Drop intel_*_supports_ccs()Nanley Chery1-124/+6
intel_tiling_supports_ccs() and intel_miptree_supports_ccs() duplicate much the work done by isl_surf_get_ccs_surf(). Drop them both and index a boolean array to choose CCS_D in intel_miptree_choose_aux_usage(). Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2019-05-14i965/miptree: Drop intel_miptree_supports_mcs()Nanley Chery1-46/+1
This function duplicates much the work done by isl_surf_get_mcs_surf(). Replace it with a simple expression. Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2019-05-14i965/miptree: Fall back to no aux if creation failsNanley Chery1-5/+6
No surface requires an auxiliary surface to operate correctly. Fall back to an uncompressed surface if mesa fails to create and allocate an auxiliary surface. This enables adding more restrictions to ISL without having to update i965. Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2019-02-15i965: Removed the field etc_format from the struct intel_mipmap_treeEleni Maria Stea1-7/+0
After the previous changes to emulate the ETC/EAC formats using the secondary shadow miptree, the etc_format field of the intel_mipmap_tree struct became redundant and the remaining check that used it has been replaced. (Nanley Chery) Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2019-02-15i965: Fixed the CopyImageSubData for ETC2 on Gen < 8Eleni Maria Stea1-17/+0
For CopyImageSubData to copy the data during the 1st draw call, we need to update the shadow tree right before the rendering. v2: - Added assertion that the miptree doesn't need update at the time we update the texture surface. (Nanley Chery) v3: - As we now update the tree before the rendering we don't need to copy the data during the unmap anymore. Removed the unnecessary update from the intel_miptree_unmap in intel_mipmap_tree.c (Nanley Chery) v4: - Fixed unrelated empty line removal (Nanley Chery) - As now the intel_upate_etc_shadow of intel_mipmap_tree.c is only called inside its following function, we don't need to declare it at the top of the file anymore. (Nanley Chery) Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2019-02-15i965: Faking the ETC2 compression on Gen < 8 GPUs using two miptrees.Eleni Maria Stea1-68/+106
GPUs Gen < 8 cannot sample ETC2 formats. So far, they converted the compressed EAC/ETC2 images to non-compressed RGBA images. When GetCompressed* functions were called, the pixels were returned in this RGBA format and not the compressed format that was expected. Trying to fix this problem, we use a secondary shadow miptree to store the decompressed data for the rendering and the main miptree to store the compressed for the Get functions to work. Each time that the main miptree is written with compressed data, we decompress them to RGB and update the shadow. Then we use the shadow for rendering. v2: - Fixes in the commit message (Nanley Chery) - Reversed the changes in brw_get_texture_swizzle and swapped the b, g values at the time that we decompress the data in the function: intel_miptree_update_etc_shadow of intel_mipmap_tree.c (Nanley Chery) - Simplified the format checks in the miptree_create function of the intel_mipmap_tree.c and reserved the call of the intel_lower_compressed_format for the case that we are faking the ETC support (Nanley Chery) - Removed the check for the auxiliary usage for the shadow miptree at creation (miptree_create of intel_mipmap_tree.c) as we won't use auxiliary buffers with these types of trees (Nanley Chery) - Set the etc_format of the non-ETC miptrees to MESA_FORMAT_NONE and removed the unecessary checks (Nanley Chery) - Fixed an unrelated indentation change (Nanley Chery) - Modified the function intel_miptree_finish_write to set the mt->shadow_needs_update to true to catch all the cases when we need to update the miptree (Nanley Chery) - In order to update the shadow miptree during the unmap of the main and always map the main (Nanley Chery) the following change was necessary: Splitted the previous update function that was updating all the mipmap levels and use two functions instead: one that updates one level and one that updates all of them. Used the first during unmap and the second before the rendering. - Removed the BRW_MAP_ETC_BIT flag and the mechanism to decide which miptree should be mapped each time and reversed all the changes in the higher level texture functions that upload data to textures as they aren't needed anymore. - Replaced the boolean needs_fake_etc with an inline function that checks when we need to fake the ETC compression (Nanley Chery) - Removed the initialization of the strides in the update function as the values will be overwritten by the intel_miptree_map call (Nanley Chery) - Used minify instead of division in the new update function intel_miptree_update_etc_shadow_levels in intel_mipmap_tree.c (Nanley Chery) - Removed the depth from the calculation of the number of slices in the new update function (intel_miptree_update_etc_shadow_levels of intel_mipmap_tree.c) as we don't need to support 3D ETC images. (Nanley Chery) v3: - Renamed the rgba_fmt in function miptree_create (intel_mipmap_tree.c) to decomp_format as the format is not always in rgba order. (Nanley Chery) - Documented the new usage for the shadow miptree in the comment above the field in the intel_miptree struct in intel_mipmap_tree.h (Nanley Chery) - Removed the redundant flags from the mapping of the miptrees in intel_miptree_update_etc_shadow of intel_mipmap_tree.c (Nanley Chery) - Fixed the switch from surface's logical level to physical level in the intel_miptree_update_etc_shadow_levels of intel_mipmap_tree.c (Nanley Chery) - Excluded the Baytrail GPUs from the check for the ETC emulation as they support the ETC formats natively. (Nanley Chery) - Simplified the check if the format is BGRA in intel_miptree_update_etc_shadow of intel_mipmap_tree.c (Nanley Chery) v4: - Removed the functions intel_miptree_(map|unmap)_etc and the check if we need to call them as with the new changes, they became unreachable. (Nanley Chery) - We'd rather calculate the level width and height using the shadow miptree instead of the main in intel_miptree_update_etc_shadow_levels of intel_mipmap_tree.c (Nanley Chery) - Fixed the format in the mt_surface_usage, set at the miptree creation, in miptree_create of intel_mipmap_tree.c (Nanley Chery) v5: - Fixed the levels calculations in intel_mipmap_tree.c (Nanley Chery) - Update the flag shadow_needs_update outside the function intel_miptree_update_etc_shadow (Nanley Chery) - Fixed indentation error (Nanley Chery) v6: - Fixed typo in commit message (Nanley Chery) - Simplified the assignment of the mt_fmt in the miptree_create of the intel_mipmap_tree.c (Nanley Chery) - Combined declarations and assignments where it was possible in the intel_miptree_update_etc_shadow and intel_miptree_update_etc_shadow_levels of the intel_mipmap_tree.c (Nanley Chery) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81843 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104272 Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2019-02-15i965: Rename intel_mipmap_tree::r8stencil_* -> ::shadow_*Nanley Chery1-8/+8
Use more generic field names. We'll reuse these fields for a workaround with ASTC miptrees. Reviewed-by: Eleni Maria Stea <estea@igalia.com>
2019-02-14drm-uapi: use local files, not system libdrmEric Engestrom1-1/+1
There was an issue recently caused by the system header being included by mistake, so let's just get rid of this include path and always explicitly #include "drm-uapi/FOO.h" Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
2019-01-10intel/isl: move tiled_memcpy static libs from i965 to islTapani Pälli1-17/+70
Patch moves intel_tiled_memcpy[_sse41] libraries to isl, renames some functions and types and makes the required build system changes for meson, automake and Android. No functional changes are introduced. v2: code cleanups, move isl_get_memcpy_type to i965 (Jason) v3: move isl_mem_copy_fn to priv header, cleanups (Jason, Dylan) Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Dylan Baker <dylan@pnwbakers.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2018-12-07intel/blorp: Expand blorp_address::offset to be 64 bits.Kenneth Graunke1-1/+1
In the softpin world, surface state base address may be a fixed 64-bit address (with no associated BO). It makes sense to store this in the offset field. But it needs to be the full size. We also update the clear color address to be consistently uint64_t everywhere so we can continue passing intel_miptree_get_clear_color a pointer to the blorp_address's offset field without type mismatches. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2018-10-23i965/miptree: Use cpu tiling/detiling when mappingScott D Phillips1-4/+106
Rename the (un)map_gtt functions to (un)map_map (map by returning a map) and add new functions (un)map_tiled_memcpy that return a shadow buffer populated with the intel_tiled_memcpy functions. Tiling/detiling with the cpu will be the only way to handle Yf/Ys tiling, when support is added for those formats. v2: Compute extents properly in the x|y-rounded-down case (Chris Wilson) v3: Add units to parameter names of tile_extents (Nanley Chery) Use _mesa_align_malloc for the shadow copy (Nanley) Continue using gtt maps on gen4 (Nanley) v4: Use streaming_load_memcpy when detiling v5: (edited by Ken) Move map_tiled_memcpy above map_movntdqa, so it takes precedence. Add intel_miptree_access_raw, needed after rebasing on commit b499b85b0f2cc0c82b7c9af91502c2814fdc8e67. v6: refactor to changes done for sse41 separation (Tapani) Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v5) Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
2018-10-12i965/miptree: Use enum instead of boolean.Rafael Antognolli1-1/+1
ISL_AUX_USAGE_NONE happens to be the same as "false", but let's do the right thing and use the enum. v2: fix intel_miptree_finish_depth too (Caio) Reviewed-by: Dylan Baker <dylan@pnwbakers.com> Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-09-26intel/isl: Add a unit suffixes to some struct fields and variablesJason Ekstrand1-33/+33
I was about to make the claim to someone that every field in isl_surf is either an enum or has explicit units. Then I looked at isl_surf and discovered this claim was wrong. We should fix that. This commit does a few refactors: * Add _B suffixes to some struct fields * Add _B to some variables and parameters * Rename row_pitch_tiles -> row_pitch_tl Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2018-09-07i965: Workaround the gen9 hw astc5x5 sampler bugJason Ekstrand1-3/+16
gen9 hardware has a bug in the sampler cache that can cause GPU hangs whenever an texture with aux compression enabled is in the sampler cache together with an ASTC5x5 texture. Because we can't control what the client binds at any given time, we have two options: resolve the CCS or decompresss the ASTC. Doing a CCS or HiZ resolve is far less drastic and will likely have a smaller performance impact. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> Tested-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2018-08-22i965/miptree: Fix can_blit_slice()Nanley Chery1-4/+3
Check the destination's row pitch against the BLT engine's row pitch limitation as well. Fixes: 0288fe8d0417730bdd5b3477130dd1dc32bdbcd3 ("i965/miptree: Use the correct BLT pitch") v2: Fix the Fixes tag (Dylan). Check the destination row pitch (Chris). Reported-by: Dylan Baker <dylan@pnwbakers.com> Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-08-22i965/miptree: Use miptree_map in map_blit functionsNanley Chery1-8/+6
This struct contains all the data of interest. can_blit_slice() will use it in the next patch to calculate the correct pitch. Suggested-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: <mesa-stable@lists.freedesktop.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-07-18i965/miptree: avoid uninitialized variable warningsCaio Marcelo de Oliveira Filho1-1/+2
GCC 8.1.1 is having a hard time identifying that the values are properly initialized when used. In the 'memset_value' case, we pass the uninitialized value to another function (that will use only if the conditions match the initialization). Just give enough hint to the compiler to figure things out. Fixes the warnings ../../src/mesa/drivers/dri/i965/intel_mipmap_tree.c: In function ‘intel_miptree_alloc_aux’: ../../src/mesa/drivers/dri/i965/intel_mipmap_tree.c:1839:18: warning: ‘memset_value’ may be used uninitialized in this function [-Wmaybe-uninitialized] mt->aux_buf = intel_alloc_aux_buffer(brw, &aux_surf, needs_memset, ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ memset_value); ~~~~~~~~~~~~~ ../../src/mesa/drivers/dri/i965/intel_mipmap_tree.c:1698:10: warning: ‘initial_state’ may be used uninitialized in this function [-Wmaybe-uninitialized] if (wants_memset) ^ ../../src/mesa/drivers/dri/i965/intel_mipmap_tree.c:1772:23: note: ‘initial_state’ was declared here enum isl_aux_state initial_state; ^~~~~~~~~~~~~ Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2018-07-13i965/miptree: Allocate MS texture BOs as BUSYNanley Chery1-2/+2
These buffer objects are never accessed with the CPU. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2018-07-13i965/miptree: Inline make_separate_stencilNanley Chery1-23/+6
Note that the separate stencil miptree now has the same alloc_flag as the depth component. Only stencil renderbuffers (as opposed to textures) have BO_ALLOC_BUSY. v2: Add note about BO_ALLOC_BUSY in message (Topi). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2018-07-13i965/miptree: Init r8stencil_needs_update to falseNanley Chery1-3/+4
The current behavior masked two bugs where the flag was not set to true after modifying the stencil texture. One case was a regression introduced with commit bdbb527a65fc729e7a9319ae67de60d03d06c3fd and another was a bug in the depthstencil mapping code. These have since been fixed. To prevent such bugs from being masked in the future, initialize r8stencil_needs_update to false. v2: Keep the delayed allocation. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2018-07-13i965/miptree: Refactor miptree_createNanley Chery1-36/+12
Enable a future patch to create the r8stencil_mt in this function. v2: Explicitly set etc_format to MESA_FORMAT_NONE (Topi). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2018-07-13i965/miptree: Add and use mt_surf_usageNanley Chery1-13/+25
v2: Make mt_fmt const (Topi). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2018-07-13i965/miptree: Share alloc_flags in miptree_createNanley Chery1-7/+4
Note that this maintains BO_ALLOC_BUSY for depth renderbuffers, but not depth textures. v2: Add note about BO_ALLOC_BUSY in message (Topi). Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2018-07-13i965/miptree: Share the miptree format in miptree_createNanley Chery1-15/+15
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2018-07-13i965/miptree: Share tiling_flags in miptree_createNanley Chery1-8/+7
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2018-07-13i965/miptree: Delete MIPTREE_CREATE_LINEARNanley Chery1-9/+2
This enum constant was introduced to enable blit maps with intel_miptree_create da2880bea05bfc87109477ab026a7f5401fc8f0c. Now that such maps use the more direct make_surface function which allows you to specify the tiling directly, the constant is no longer being used. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2018-07-13i965/miptree: Use make_surface in map_blitNanley Chery1-6/+6
Do this so that we don't have to special case linearly-tiled depth buffers in miptree_create. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>