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path: root/src/mesa/drivers/dri/i965/gen7_misc_state.c
AgeCommit message (Expand)AuthorFilesLines
2017-08-30i965: drop brw->is_haswell in favor of devinfo->is_haswellLionel Landwerlin1-1/+2
2017-08-04i965: Reduce passing 2x32b of reloc_domains to 2 bitsChris Wilson1-10/+3
2017-07-22i965/miptree: Clean-up unusedTopi Pohjolainen1-6/+2
2017-07-20i965/miptree: Represent w-tiled stencil surfaces with islTopi Pohjolainen1-2/+6
2017-07-20i965/miptree: Switch to isl_surf::row_pitchTopi Pohjolainen1-2/+2
2017-07-20i965/miptree: Take interleaving into account in stencil pitchTopi Pohjolainen1-11/+1
2017-06-22mesa: replace _mesa_update_stencil() with helper functionsMarek Olšák1-1/+1
2017-06-19i965/miptree/gen7+: Use isl for hiz layoutsTopi Pohjolainen1-3/+2
2017-06-07i965/miptree: Store fast clear colors in an isl_color_valueJason Ekstrand1-1/+6
2016-11-18i965: Disable depth writes when depth test is GL_EQUAL.Kenneth Graunke1-1/+1
2016-11-08i965/miptree: Create a hiz mcs typeBen Widawsky1-3/+3
2016-08-26i965: Track that the stencil data was updated when renderingJordan Justen1-0/+1
2016-05-25i965: Assert that a depth_mt exists when using HiZ.Matt Turner1-0/+1
2016-04-23i965: Make all atoms to track BRW_NEW_BLORP by defaultKenneth Graunke1-1/+2
2015-06-24i965: Rename intel_emit* to reflect their new location in brw_pipe_controlChris Wilson1-1/+1
2015-03-09i965/gen7: Don't rely directly on the hiz miptree structureJordan Justen1-3/+4
2015-03-09i965/hiz: Start to separate miptree out from hiz buffersJordan Justen1-1/+1
2014-12-02i965: Delete brw_state_flags::cache and related code.Kenneth Graunke1-1/+0
2014-11-29i965: Alphabetize brw_tracked_state flags and use a consistent style.Kenneth Graunke1-1/+3
2014-05-13i965/gen7 depth: Set depth size based on LOD0 for 3D texturesJordan Justen1-2/+2
2014-05-09i965/Gen7: Set up layer constraints properly for depth buffersChris Forbes1-9/+6
2014-05-01i965: Delete the intel_regions.c code.Eric Anholt1-1/+0
2014-05-01i965: Drop use of intel_region from miptrees.Eric Anholt1-6/+6
2014-04-11i965/gen7: Skip repeated NULL depth/stencil state emits.Eric Anholt1-0/+8
2014-01-10i965: Fix clears of layered framebuffers with mismatched layer counts.Paul Berry1-1/+1
2013-11-21mesa: Track number of layers in layered framebuffers.Paul Berry1-1/+1
2013-10-07gen7: Use logical, not physical, dims in 3DSTATE_DEPTH_BUFFER (v2)Chad Versace1-2/+2
2013-08-21i965/gen7: Set MOCS L3 cacheability for IVB/BYT (v2)Ville Syrjälä1-1/+1
2013-08-04gen7 depth surface: program 3DSTATE_DEPTH_BUFFER to top of surfaceJordan Justen1-8/+28
2013-08-04gen7 depth surface: calculate minimum array element being renderedJordan Justen1-0/+10
2013-08-04gen7 depth surface: calculate LOD being rendered toJordan Justen1-0/+3
2013-08-04gen7 depth surface: calculate depth (array size) for depth surfaceJordan Justen1-0/+3
2013-08-04gen7 depth surface: calculate more specific surface typeJordan Justen1-0/+31
2013-07-18i965/hsw: Change L3 MOCS for depth, hiz, and stencilChad Versace1-2/+5
2013-07-15i965: Cite the Sandybridge PRM for Gen7 stencil pitch requirements.Kenneth Graunke1-9/+5
2013-07-09i965: Delete intel_context entirely.Kenneth Graunke1-2/+1
2013-07-09i965: Move intel_context::is_<platform> flags to brw_context.Kenneth Graunke1-1/+1
2013-07-09i965: Pass brw_context to functions rather than intel_context.Kenneth Graunke1-1/+1
2013-06-25i965: Remove _NEW_DEPTH state flagging on drawbuffers change.Eric Anholt1-1/+1
2013-04-10intel: Replace checks for hiz_mt with intel_has*hiz()Chad Versace1-5/+6
2013-04-04i965: Fix stencil write enable flag in 3DSTATE_DEPTH_BUFFER on Gen7+.Kenneth Graunke1-1/+1
2013-04-02i965: Reduce code duplication in handling of depth, stencil, and HiZ.Paul Berry1-62/+31
2013-01-18intel: Make intel_region's pitch be bytes instead of pixels.Eric Anholt1-3/+3
2012-11-19i965: Move all the depth/stencil/hiz offset logic into the workaround.Eric Anholt1-79/+11
2012-10-16i965: Fix rendering to small mipmaps of depth/stencil buffers using a temp mt.Eric Anholt1-60/+40
2012-10-16i965: Share the draw x/y offset masking code between main/blorp and all gens.Eric Anholt1-36/+5
2012-09-12intel: Add map_stencil_as_y_tiled to intel_region_get_aligned_offset.Paul Berry1-2/+4
2012-09-12intel: Add map_stencil_as_y_tiled to intel_region_get_tile_masks.Paul Berry1-2/+3
2012-05-23i965/gen6+: Add support for fast depth clears.Eric Anholt1-2/+2
2012-05-14i965/gen7: Set tile_x/y to 0 in the no-stencil case.Eric Anholt1-1/+1
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