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2017-07-22anv/image: zalloc image viewsJason Ekstrand1-7/+1
This allows us to avoid some extra zeroing. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-07-22anv/image: Use vk_zalloc instead of an explicit memsetJason Ekstrand1-3/+2
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-07-22anv: Separate surface states by layout instead of aux_usageJason Ekstrand4-53/+58
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-07-22intel/isl: Add some sanity checks for compressed surfacesJason Ekstrand1-0/+18
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-07-22intel/isl: Add a helper to get a subimage surfaceJason Ekstrand3-30/+76
We already have a helper for doing this in BLORP, this just moves the logic into ISL where we can share it with other components. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-07-22anv: Get rid of some unused function declarationsJason Ekstrand1-7/+0
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-07-22intel/isl: Add a helper for determining if a color is 0/1Jason Ekstrand2-0/+30
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-07-22intel/blorp: Allow blorp_copy on sRGB formatsJason Ekstrand1-2/+16
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-07-22intel/isl/format: Add an srgb_to_linear helperJason Ekstrand2-1/+53
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-07-22intel/isl/format: Dedent the template in gen_format_layout.pyJason Ekstrand1-58/+57
This makes it much easier to edit the template and doesn't really dirty the python all that much. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-07-22intel/isl: Add an aux state for "partial clear"Jason Ekstrand1-35/+53
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-07-22intel/blorp: Add a partial resolve pass for MCSJason Ekstrand4-1/+213
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-07-22anv: Predicate fast-clear resolvesNanley Chery3-16/+120
Image layouts only let us know that an image *may* be fast-cleared. For this reason we can end up with redundant resolves. Testing has shown that such resolves can measurably hurt performance and that predicating them can avoid the penalty. v2: - Introduce additional resolve state management function (Jason Ekstrand). - Enable easy retrieval of fast clear state fields. v3: Use more descriptive field enums (Jason) Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-07-22intel/blorp: Allow BLORP calls to be predicatedNanley Chery2-0/+6
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-07-22anv/cmd_buffer: Skip some input attachment transitionsNanley Chery1-5/+26
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-07-22anv: Stop resolving CCS implicitlyNanley Chery3-169/+5
With an earlier patch from this series, resolves are additionally performed on layout transitions. Remove the now unnecessary implicit resolves within render passes. Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-07-22anv: Transition more color buffer layoutsNanley Chery2-28/+169
v2: Expound on comment for the pipe controls (Jason Ekstrand). v3: - Cast base_layer to uint64_t to avoid overflow. - Remove "seems" from the pipe control comment. - Fix clamp of layer_count (Jason Ekstrand). Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-07-22anv/cmd_buffer: Warn about not enabling CCS_ENanley Chery1-5/+7
Use the performance warning infrastructure to provide helpful information when testing applications. Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-07-22anv/cmd_buffer: Move aux_usage assignment upNanley Chery1-32/+30
For readability, bring the assignment of CCS closer to the assignment of NONE and MCS. Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-07-22anv/cmd_buffer: Always enable CCS_D in render passesNanley Chery2-11/+20
The lifespan of the fast-clear data will surpass the render pass scope. We need CCS_D to be enabled in order to invalidate blocks previously marked as cleared and to sample cleared data correctly. v2: Avoid refactoring. v3: Allow CCS_D for subpass resolves. Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-07-22anv/cmd_buffer: Disable CCS on gen7 color attachments upfrontNanley Chery1-11/+5
The next patch enables the use of CCS_D even when the color attachment will not be fast-cleared. Catch the gen7 case early to simplify the changes required. Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-07-22anv/cmd_buffer: Ensure fast-clear values are currentNanley Chery1-0/+114
v2: Rewrite functions, change location of synchronization. Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-07-22anv/gpu_memcpy: Add a lighter-weight GPU memcpy functionNanley Chery2-0/+45
We'll be performing a GPU memcpy in more places to copy small amounts of data. Add an alternate function that thrashes less state. v2: - Make a new function (Jason Ekstrand). - Move the #define into the function. v3: - Update the function name (Jason). - Update comments. v4: Use an indirect drawing register as TEMP_REG (Jason Ekstrand). Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-07-22anv/cmd_buffer: Restrict fast clears in the GENERAL layoutNanley Chery3-0/+40
v2: Remove ::first_subpass_layout assertion (Jason Ekstrand). v3: Allow some fast clears in the GENERAL layout. v4: Remove extra '||' and adjust line break (Jason Ekstrand). Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-07-22anv/cmd_buffer: Don't partially fast clear image layersNanley Chery1-8/+23
v2: Don't pass in the command buffer (Jason Ekstrand). v3: Remove an incorrect assertion and an if condition for gen7. Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-07-22anv/cmd_buffer: Initialize the clear values bufferNanley Chery1-1/+78
v2: Rewrite functions. v3 (Jason Ekstrand): - Don't set ResourceMinLOD. - Fix clamp of level_count. Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-07-22anv/image: Append CCS/MCS with a fast-clear state bufferNanley Chery2-0/+90
v2: Update comments, function signatures, and add assertions. Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-07-22anv/image: Disable CCS if the image doesn't support renderingNanley Chery1-0/+15
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-07-22intel/isl: Add surface state clear value informationNanley Chery2-0/+13
This will be used to load and store clear values from surface state objects. Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-07-22anv: Transition MCS buffers from the undefined layoutNanley Chery3-18/+35
v2: Define MCS buffers with any sample count (Jason) Cc: <mesa-stable@lists.freedesktop.org> Suggested-by: Jason Ekstrand <jason@jlekstrand.net> Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
2017-07-22intel/isl: Tighten up restrictions for CCS on gen7Jason Ekstrand1-7/+23
It may technically be possible to enable some sort of fast-clear support for at least the base slice of a 2D array texture on gen7. However, it's not documented to work, we've never tried to do it in GL, and we have no idea what the hardware does if you turn on CCS_D with arrayed rendering. Let's just play it safe and disallow it for now. If someone really cares that much about gen7 performance, they can come along and try to get it working later.
2017-07-22anv/blorp: Assert isl_surf_init success in do_buffer_copyJason Ekstrand1-13/+15
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-07-22anv/blorp: Explicitly set row_pitch in do_buffer_copyJason Ekstrand1-1/+1
We have a very specific row pitch that we want and we don't want ISL to be changing it on us so just be explicit about it. Fixes: a40f0430347c07bf2d5794642fe02f5dd248a473 Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-07-21i965: Set lower_vote_trivial in vector_nir_options_gen6 too.Kenneth Graunke1-0/+1
There's a second struct for Gen6+. Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-07-22intel/isl/gen7: Don't allow multisampled surfaces with valign2Topi Pohjolainen1-19/+23
There is the same constraintg later on as assert in isl_gen7_choose_image_alignment_el() so catch it earlier in order to return error instead of crash. Needed to avoid crashes with piglits on IVB and HSW: arb_internalformat_query2.image_format_compatibility_type pname checks arb_internalformat_query2.all internalformat_<x>_type pname checks arb_internalformat_query2.max dimensions related pname checks arb_copy_image.arb_copy_image-formats --samples=2/4/6/8 arb_texture_float.multisample-fast-clear gl_arb_texture_float Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-07-22intel/isl/gen7: Allow msaa with signed integer formatsTopi Pohjolainen1-2/+3
These formats are already allowed by the i965 GL driver, and the feature seems to work just fine. There are tests for multisampled rendering in piglit: tests/spec/ext_framebuffer_multisample which can be patched to try 16I/32I in addition to GL_RGBA8I. IvyBridge passed all tests with all sample numbers. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-07-22intel/isl/gen7: Allow msaa with 128-bit formatsTopi Pohjolainen1-4/+7
These formats are already allowed by the i965 GL driver, and the feature seems to work just fine. There are tests for multisampled rendering in piglit: tests/spec/ext_framebuffer_multisample which can be patched to try GL_RGBA16F/32F/16I/16UI/32I/32UI in addition to GL_RGBA/8I. IvyBridge passed all tests with all sample numbers and even with 128-bit formats. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-07-22intel/isl: Allow 1D surfaces with compressed formatsTopi Pohjolainen1-1/+1
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-07-22intel/isl: Align non-tiled horizontally by cache lineTopi Pohjolainen1-1/+15
in order to support blit engine. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-07-20i965/fs: Match destination type to size for ballotMatt Turner2-2/+6
No use in taking a 64-bit value when we know the high 32-bits are zero.
2017-07-20nir: Reduce destination size of ballot intrinsic when possibleMatt Turner1-0/+1
Some hardware, like i965, doesn't support group sizes greater than 32. In that case, we can reduce the destination size of the ballot intrinsic, which will simplify our code generation. Reviewed-by: Connor Abbott <cwabbott0@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-07-20i965/fs: Implement ARB_shader_ballot operationsMatt Turner3-0/+48
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-07-20i965/fs: Do not move MOVs writing the flag outside of control flowMatt Turner1-2/+4
The implementation of ballotARB() will start by zeroing the flags register. So, a doing something like if (gl_SubGroupInvocationARB % 2u == 0u) { ... = ballotARB(true); [...] } else { ... = ballotARB(true); [...] } (like fs-ballot-if-else.shader_test does) would generate identical MOVs to the same destination (the flag register!), and we definitely do not want to pull that out of the control flow. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-07-20i965/fs: Handle explicit flag sources in flags_read()Francisco Jerez1-4/+5
The implementations of the ARB_shader_ballot intrinsics will explicitly read the flag as a source register. Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-07-20nir: Add system values from ARB_shader_ballotMatt Turner2-3/+3
We already had a channel_num system value, which I'm renaming to subgroup_invocation to match the rest of the new system values. Note that while ballotARB(true) will return zeros in the high 32-bits on systems where gl_SubGroupSizeARB <= 32, the gl_SubGroup??MaskARB variables do not consider whether channels are enabled. See issue (1) of ARB_shader_ballot. Reviewed-by: Connor Abbott <cwabbott0@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-07-20i965/fs: Implement ARB_shader_group_vote operationsMatt Turner1-0/+50
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-07-20i965/fs: Handle explicit flag destinations in flags_written()Francisco Jerez1-4/+19
The implementations of the ARB_shader_group_vote intrinsics will explicitly write the flag as the destination register. Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-07-20i965/vec4: Lower ARB_shader_group_vote intrinsicsMatt Turner1-0/+1
I don't expect anyone is going to care about using this in vec4 programs (vertex/tessellation/geometry on Gen6/7), no one has come up with a good way to implement it much less test it. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-07-20nir: Add pass to optimize intrinsicsMatt Turner1-0/+1
Specifically, constant fold intrinsics from ARB_shader_group_vote, but I suspect it'll be useful for other things in the future. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-07-20intel/isl/gen4: Represent cube maps with 3D layoutTopi Pohjolainen1-6/+35
v2 (Jason): Check for !ISL_SURF_DIM_3D instead of CUBE_BIT. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>