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2017-06-29android: anv: drop libdrm_intel dependencyMauro Rossi1-1/+2
In addition to Rob Herring "Android: i965: remove libdrm_intel dependency", we can drop libdrm_intel dependency in anv for Android. Please check if libdrm has to stay as shared dependency and drop this comment line. Fixes: 7dd20bc ("anv/i965: drop libdrm_intel dependency completely") Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-06-29anv: use devinfo for number of thread/euLionel Landwerlin1-2/+3
It turns out Gen9LP has fewer threads per EU (6 vs 7). Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
2017-06-29intel: tools: add intel_aub.h as part of aubinatorJuan A. Suarez Romero1-1/+2
Include intel_aub.h in the Makefile.tools.am Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-06-29intel: automake: include Makefile.drm.amJuan A. Suarez Romero1-0/+1
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-06-28genxml: Silence about a billion unused parameter warningsIan Romanick1-2/+7
v2: Use textwrap.dedent to make the source line a lot shorter. Shortening (?) the line was requested by Jason. v3: Simplify the texwrap.dedent usage. Suggested by Dylan. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2017-06-27anv/i965: drop libdrm_intel dependency completelyLionel Landwerlin9-2/+3565
With Ken's work to drop the library dependency on libdrm_intel, we now only depend on libdrm for the kernel uapi headers it provides. It seems like we're better off just embeddeding those headers ourselves, making the lives of people developping news features tightly integrated with the kernel a tiny bit easier. This change also makes it a bit more obvious what cflags/libs are required by the i915 drivers vs i965, by renaming INTEL_CFLAGS/LIBS into I915_CFLAGS/LIBS. Headers were generated from drm-tip on the following commit : commit 6d61e70ccc21606ffb8a0a03bd3aba24f659502b Merge: 338ffbf7cb5e c0bc126f97fb Author: Dave Airlie <airlied@redhat.com> Date: Tue Jun 27 07:24:49 2017 +1000 Backmerge tag 'v4.12-rc7' into drm-next v2: Use installed files from the kernel (Daniel Vetter) v3: Use headers from drm-next rather than drm-tip (Dave/Daniel) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-27aubinator: import intel_aub.h from libdrmLionel Landwerlin1-0/+153
This enables us to compile aubinator without the libdrm dependency. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-27intel/anv: Add missing break in anv_CreateDevice()Topi Pohjolainen1-0/+1
CID: 1413018 Reviewed-by: Eric Engestrom <eric@engestrom.ch> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-06-26blorp: Use normalized coordinates on Gen6Ian Romanick2-5/+8
Apparently, the sampler has some sort of precision issues for non-normalized texture coordinates with linear filtering. This caused some small precision issues in scaled blits. Work around this by using normalized coordinates. There is some extra work necessary because Gen6 uses TEX (instead of TXF) for some multisample resolve blits. Fixes piglit.spec.arb_framebuffer_object.fbo-blit-stretch on SNB. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68365 Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
2017-06-26anv/gpu_memcpy: Rename the gpu_memcpy functionNanley Chery3-11/+11
A GPU memcpy function could alternatively be implemented using MI_* commands. Provide more detail into how this one operates in case another memcpy function is created. v2: - Update the commit message. v3: - Use 'memcpy' instead of 'cpy' (Jason Ekstrand) - Shorten 'streamout' to 'so' Suggested-by: Jason Ekstrand <jason@jlekstrand.net> Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> (v2) Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-26anv/blorp: Provide surface states for CCS resolvesNanley Chery1-19/+10
In the future, we plan on using this method to resolve images whose surface state fast-clear value is dynamically updated during command buffer execution. Start using it now for testing and to reduce churn later on. Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-26anv/blorp: Add a surface-state-based CCS resolve functionNanley Chery2-0/+44
This will be used in the next patch. v2: - Omit BLORP_BATCH_NO_EMIT_DEPTH_STENCIL (Jason Ekstrand) - Update commit message. Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-26blorp/clear: Add a binding-table-based CCS resolve functionNanley Chery2-17/+57
v2: - Do layered resolves. (Jason Ekstrand): - Replace "bt" suffix with "attachment". - Rename helper function to prepare_ccs_resolve. - Move blorp_params_init() into helper function. Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-26anv: Adjust params of color buffer transitioning functionsNanley Chery3-36/+39
Splitting out these fields will make the color buffer transitioning function simpler when it gains more features. v2: Remove unintended blank line (Iago Toral) Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-26anv/blorp: Remove 3D subresource transition workaroundNanley Chery1-4/+4
For 3D image subresources undergoing a layout transition via PipelineBarrier, we increase the number of fast-cleared layers to match the intended behaviour of KHR_maintenance1. When such subresources undergo layout transitions between subpasses, we don't do this to avoid failing incorrect CTS tests. Instead, unify the behaviour in both scenarios, and wait for the CTS tests to catch up. See CL 1111 for the test fix and Vulkan issue #849 for more information. On SKL+, this causes 3 test failures under: dEQP-VK.pipeline.render_to_image.3d.* v2: Add a reference to the Vulkan issue (Iago Toral). Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> (v1) Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-26anv/cmd_buffer: Adjust the image view reloc functionNanley Chery1-20/+25
Make the function take in an image instead of an image view. This enables us to record relocations for surfaces states created outside of the anv_CreateImageView path. v2 (Jason Ekstrand): - Use image->offset instead of surf_offset in aux_offset calculation. Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-26anv/cmd_buffer: Adjust layout transition aspect checkingNanley Chery1-5/+3
Reflect the fact that an image view or subresource range with the color aspect cannot have any other aspect. Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-26anv: Add and use color auxiliary buffer helpersNanley Chery2-0/+32
v2: - Check for aux levels in layer helper (Jason Ekstrand) - Don't assert aux is present, return 0 if it isn't. - Use the helpers. v3: - Make the helpers aspect-agnostic (Jason Ekstrand) - Drop anv_image_has_color_aux() Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> (v2) Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-26intel/isl: Only create a CCS buffer if the image supports renderingNanley Chery1-1/+1
v2: Omit the commit message. Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-26intel/isl: Limit CCS to one level and layer on gen7Nanley Chery1-2/+7
v2 (Jason Ekstrand): - Remove Vulkan-specific terminology from the commit title. - Replace '== 7' with '<= 7' to hint that this is a new feature on BDW+. Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> (v1) Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-26intel/blorp: Check for layer fast-clear restrictionNanley Chery1-0/+5
v2: Update commit title (Jason Ekstrand) Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> (v1) Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-26intel/blorp: Assert levels and layers are in rangeNanley Chery2-4/+7
v2 (Jason Ekstrand): - Update commit title. - Check aux level and layer as well. v3 (Jason Ekstrand): - Move the non-aux layer check. Signed-off-by: Nanley Chery <nanley.g.chery@intel.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> (v1) Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-26anv: use Mesa's u_atomic.h headerEric Engestrom1-2/+3
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-23anv/cnl: Don't write to Cache Mode Register 1 on gen10+Anuj Phogat1-3/+1
For PartialResolveDisableInVC field recommendation is to always set this to 0 and that's the default value of the bit. So, we have nothing left to write to CACHE_MODE_1. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-22genxml: fix gen5 sampler border color state.Rafael Antognolli1-20/+20
Based on the current code, gen5 and gen6 have the same sampler border color state struct. So fix the gen5 one to match gen6. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-06-22aubinator: Dump sampler state pointers on gen6 too.Rafael Antognolli1-0/+11
We already have a function to dump sampler states, so do that for gen6 too. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-06-22anv: Fix -Wswitch in anv_layout_to_aux_usage()Chad Versace1-0/+3
anv_layout_to_aux_usage() lacked a case for VK_IMAGE_LAYOUT_SHARED_PRESENT_KHR. Add an unreachable case, because we don't support the extension. Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-22i965/CFL: Add PCI Ids for Coffee Lake.Anusha Srivatsa2-0/+27
Coffee Lake has a gen9 graphics following KBL. From 3D perspective, CFL is a clone of KBL/SKL features. v2: Change commit message, correct alignment <Anuj Phogat> v3: Update IDs. v4: Initialize l3_banks, correct nomenclature <Anuj> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Acked-by: Benjamin Widawsky <benjamin.widawsky@intel.com> Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2017-06-22intel: Enable vulkan build for gen10Anuj Phogat1-0/+4
This patch just enables building Vulkan libs for gen10. We still don't have gen 10 support enabled on Vulkan. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-22anv/cnl: Generate and use gen10 functionsAnuj Phogat4-1/+13
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-22anv/cnl: Don't set FloatBlendOptimizationEnable{Mask}Anuj Phogat1-3/+6
This field is remove from CACHE_MODE_1 register in gen10. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-22anv/cnl: Use GENX(xx) in place of GEN9_xxAnuj Phogat1-8/+8
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-22anv/cnl: Add #defines for MOCS and genX(x)Anuj Phogat1-0/+14
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-22intel/genxml: Add Gen10 CACHE_MODE_1 definitionsAnuj Phogat1-0/+18
Few of the fields in this register are changed as compared to gen9.xml. V2: Remove some fields which are not valid anymore. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2017-06-22intel/genxml: Rename StartInstanceLocation to StartingInstanceLocationAnuj Phogat1-1/+1
This is required because we already have a macro defined with the name StartInstanceLocation. Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2017-06-22intel/genxml: Rename IndirectStatePointer to BorderColorPointerAnuj Phogat1-1/+1
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2017-06-22intel/genxml: Combine DataDWord{0, 1} fields in to ImmediateData fieldAnuj Phogat1-2/+1
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2017-06-22intel/genxml: Add INSTDONE registers in gen10Anuj Phogat1-0/+115
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2017-06-22intel/genxml: Add better support for MI_MATH in gen10Anuj Phogat1-4/+65
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2017-06-22anv: FORMAT_FEATURE_TRANSFER_SRC/DST_BIT_KHR not used with ↵Andres Gomez1-5/+0
VkFormatProperties.bufferFeatures VK_FORMAT_FEATURE_TRANSFER_[SRC|DST]_BIT_KHR is a flag value of the VkFormatFeatureFlagBits enum that can only be hold and checked against the linearTilingFeatures or optimalTilingFeatures members of the VkFormatProperties struct but not the bufferFeatures member. >From the Vulkan® 1.0.51, with the VK_KHR_maintenance1 extension, section 32.3.2 docs for VkFormatProperties: "* linearTilingFeatures is a bitmask of VkFormatFeatureFlagBits specifying features supported by images created with a tiling parameter of VK_IMAGE_TILING_LINEAR. * optimalTilingFeatures is a bitmask of VkFormatFeatureFlagBits specifying features supported by images created with a tiling parameter of VK_IMAGE_TILING_OPTIMAL. * bufferFeatures is a bitmask of VkFormatFeatureFlagBits specifying features supported by buffers." ... Bits which can be set in the VkFormatProperties features linearTilingFeatures, optimalTilingFeatures, and bufferFeatures are: typedef enum VkFormatFeatureFlagBits { ... VK_FORMAT_FEATURE_TRANSFER_SRC_BIT_KHR = 0x00004000, VK_FORMAT_FEATURE_TRANSFER_DST_BIT_KHR = 0x00008000, ... } VkFormatFeatureFlagBits; ... The following bits may be set in linearTilingFeatures and optimalTilingFeatures, specifying that the features are supported by images or image views created with the queried vkGetPhysicalDeviceFormatProperties::format: ... * VK_FORMAT_FEATURE_TRANSFER_SRC_BIT_KHR specifies that an image can be used as a source image for copy commands. * VK_FORMAT_FEATURE_TRANSFER_DST_BIT_KHR specifies that an image can be used as a destination image for copy commands and clear commands." Cc: Jason Ekstrand <jason.ekstrand@intel.com> Cc: Iago Toral Quiroga <itoral@igalia.com> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Signed-off-by: Andres Gomez <agomez@igalia.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-06-21intel/genxml: Use the same naming convention for Floating Point Mode.Rafael Antognolli1-2/+2
In newer gens, this field has a prefix and the non-IEEEE-745 mode is called "Alternate", instead of simply "Alt". Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-21intel/genxml: Normalize URB Data field in WM_STATE.Rafael Antognolli3-3/+3
On gen6+, this is called "Dispatch GRF Start Register For Constant/Setup Data 0", while on gen5 and lower it's called only "Dispatch GRF Start Register For URB Data", but it's essentially the same thing (URB data), so rename it to match newer gens and simplify the C code that handles it. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-21intel/genxml: Rename field on WM_STATE to match gen6+.Rafael Antognolli3-3/+3
"Pixel Shader Kill Pixel" -> "Pixel Shader Kills Pixel", which is how it's called on newer gens. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-21intel/genxml: Normalize fields on WM_STATE.Rafael Antognolli2-4/+4
On gen4, WM_STATE only has one Kernel Start Pointer and one GRF Register Count, but we can make the code that handles this on multiple gens simpler if we add an index 0 to it too. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-21intel/genxml: Add missing field to CLIP_STATE.Rafael Antognolli2-0/+5
Just because it's not set doesn't mean that it doesn't exist. And since the field is there on newer gens, having it on gen5 simplifies the code when porting gen5 and lower. Also add missing value to API Mode on CLIP_STATE on gen4. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-21intel/genxml: Fix type of UserClipFlags ClipTest Enable Bitmask.Rafael Antognolli3-3/+3
This is a bitmask, so it can't be a boolean. Also rename it so it matches gen6+. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-21intel/genxml: Add missing fields to CLIP_STATE on gen4-5.Rafael Antognolli2-0/+2
These fields are set by brw_clip_unit, so we need them when converting to genxml. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-21intel/genxml: Normalize GS_STATE.Rafael Antognolli1-1/+1
Rename "Rendering Enable" to "Rendering Enabled", so it matches gen6+. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-20intel: compiler/i965: fix is_broxton checksLionel Landwerlin5-6/+9
In 5f2fe9302c is_geminilake was introduced for the differenciate broxton from geminilake. Unfortunately I failed as verifying that is_broxton is throughout the code base to mean Gen9lp. Fixes: 5f2fe9302c ("intel: common: add flag to identify platforms by name") Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-20i965/cnl: Add l3 configuration for CannonlakeBen Widawsky1-1/+20
V2 (Anuj): Squash the changes in one patch rebase on master. Address the review comments made by Francisco Jerez. Do the URB allocation per slice (not per bank). V3 (Anuj): Update the comment. Format the table as other l3 config tables. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net> --- V1 was sent out with the heading: "i965/cnl: Properly handle l3 configuration"