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path: root/src/intel
AgeCommit message (Expand)AuthorFilesLines
2017-06-29android: anv: drop libdrm_intel dependencyMauro Rossi1-1/+2
2017-06-29anv: use devinfo for number of thread/euLionel Landwerlin1-2/+3
2017-06-29intel: tools: add intel_aub.h as part of aubinatorJuan A. Suarez Romero1-1/+2
2017-06-29intel: automake: include Makefile.drm.amJuan A. Suarez Romero1-0/+1
2017-06-28genxml: Silence about a billion unused parameter warningsIan Romanick1-2/+7
2017-06-27anv/i965: drop libdrm_intel dependency completelyLionel Landwerlin9-2/+3565
2017-06-27aubinator: import intel_aub.h from libdrmLionel Landwerlin1-0/+153
2017-06-27intel/anv: Add missing break in anv_CreateDevice()Topi Pohjolainen1-0/+1
2017-06-26blorp: Use normalized coordinates on Gen6Ian Romanick2-5/+8
2017-06-26anv/gpu_memcpy: Rename the gpu_memcpy functionNanley Chery3-11/+11
2017-06-26anv/blorp: Provide surface states for CCS resolvesNanley Chery1-19/+10
2017-06-26anv/blorp: Add a surface-state-based CCS resolve functionNanley Chery2-0/+44
2017-06-26blorp/clear: Add a binding-table-based CCS resolve functionNanley Chery2-17/+57
2017-06-26anv: Adjust params of color buffer transitioning functionsNanley Chery3-36/+39
2017-06-26anv/blorp: Remove 3D subresource transition workaroundNanley Chery1-4/+4
2017-06-26anv/cmd_buffer: Adjust the image view reloc functionNanley Chery1-20/+25
2017-06-26anv/cmd_buffer: Adjust layout transition aspect checkingNanley Chery1-5/+3
2017-06-26anv: Add and use color auxiliary buffer helpersNanley Chery2-0/+32
2017-06-26intel/isl: Only create a CCS buffer if the image supports renderingNanley Chery1-1/+1
2017-06-26intel/isl: Limit CCS to one level and layer on gen7Nanley Chery1-2/+7
2017-06-26intel/blorp: Check for layer fast-clear restrictionNanley Chery1-0/+5
2017-06-26intel/blorp: Assert levels and layers are in rangeNanley Chery2-4/+7
2017-06-26anv: use Mesa's u_atomic.h headerEric Engestrom1-2/+3
2017-06-23anv/cnl: Don't write to Cache Mode Register 1 on gen10+Anuj Phogat1-3/+1
2017-06-22genxml: fix gen5 sampler border color state.Rafael Antognolli1-20/+20
2017-06-22aubinator: Dump sampler state pointers on gen6 too.Rafael Antognolli1-0/+11
2017-06-22anv: Fix -Wswitch in anv_layout_to_aux_usage()Chad Versace1-0/+3
2017-06-22i965/CFL: Add PCI Ids for Coffee Lake.Anusha Srivatsa2-0/+27
2017-06-22intel: Enable vulkan build for gen10Anuj Phogat1-0/+4
2017-06-22anv/cnl: Generate and use gen10 functionsAnuj Phogat4-1/+13
2017-06-22anv/cnl: Don't set FloatBlendOptimizationEnable{Mask}Anuj Phogat1-3/+6
2017-06-22anv/cnl: Use GENX(xx) in place of GEN9_xxAnuj Phogat1-8/+8
2017-06-22anv/cnl: Add #defines for MOCS and genX(x)Anuj Phogat1-0/+14
2017-06-22intel/genxml: Add Gen10 CACHE_MODE_1 definitionsAnuj Phogat1-0/+18
2017-06-22intel/genxml: Rename StartInstanceLocation to StartingInstanceLocationAnuj Phogat1-1/+1
2017-06-22intel/genxml: Rename IndirectStatePointer to BorderColorPointerAnuj Phogat1-1/+1
2017-06-22intel/genxml: Combine DataDWord{0, 1} fields in to ImmediateData fieldAnuj Phogat1-2/+1
2017-06-22intel/genxml: Add INSTDONE registers in gen10Anuj Phogat1-0/+115
2017-06-22intel/genxml: Add better support for MI_MATH in gen10Anuj Phogat1-4/+65
2017-06-22anv: FORMAT_FEATURE_TRANSFER_SRC/DST_BIT_KHR not used with VkFormatProperties...Andres Gomez1-5/+0
2017-06-21intel/genxml: Use the same naming convention for Floating Point Mode.Rafael Antognolli1-2/+2
2017-06-21intel/genxml: Normalize URB Data field in WM_STATE.Rafael Antognolli3-3/+3
2017-06-21intel/genxml: Rename field on WM_STATE to match gen6+.Rafael Antognolli3-3/+3
2017-06-21intel/genxml: Normalize fields on WM_STATE.Rafael Antognolli2-4/+4
2017-06-21intel/genxml: Add missing field to CLIP_STATE.Rafael Antognolli2-0/+5
2017-06-21intel/genxml: Fix type of UserClipFlags ClipTest Enable Bitmask.Rafael Antognolli3-3/+3
2017-06-21intel/genxml: Add missing fields to CLIP_STATE on gen4-5.Rafael Antognolli2-0/+2
2017-06-21intel/genxml: Normalize GS_STATE.Rafael Antognolli1-1/+1
2017-06-20intel: compiler/i965: fix is_broxton checksLionel Landwerlin5-6/+9
2017-06-20i965/cnl: Add l3 configuration for CannonlakeBen Widawsky1-1/+20