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AgeCommit message (Expand)AuthorFilesLines
2018-07-04i965: Fix output register sizes when variable ranges are interleavedNeil Roberts1-7/+18
2018-07-02i965/vec4: Don't cmod propagate from CMP to ADD if the writemask isn't compat...Ian Romanick2-5/+87
2018-07-02intel/compiler: Silence unused parameter warnings brw_nir.cIan Romanick5-7/+6
2018-07-02anv: Add support for the on-disk shader cacheJason Ekstrand3-11/+126
2018-07-02anv/pipeline_cache: Add a _locked suffix to a functionJason Ekstrand1-14/+15
2018-07-02anv: Add device-level helpers for searching for and uploading kernelsJason Ekstrand3-79/+98
2018-07-02anv/pipeline: Stop optimizing for not having a cacheJason Ekstrand1-34/+31
2018-07-02anv: Use a default pipeline cache if none is specifiedJason Ekstrand5-18/+25
2018-07-02anv: Be more careful about hashing pipeline layoutsJason Ekstrand1-3/+38
2018-07-02anv,intel: Enable nir_opt_large_constants for VulkanJason Ekstrand3-0/+14
2018-07-02anv: Add state setup support for shader constantsJason Ekstrand3-19/+101
2018-07-02anv: Add support for shader constant data to the pipeline cacheJason Ekstrand4-0/+50
2018-07-02anv/cmd_buffer: make descriptors dirty when emitting base state addressIago Toral Quiroga1-0/+5
2018-07-02anv/cmd_buffer: clean dirty push constants flag after emitting push constantsIago Toral Quiroga1-0/+2
2018-07-02anv/cmd_buffer: never shrink the push constant buffer sizeIago Toral Quiroga1-1/+16
2018-06-29anv: finish the binding_table_pool on destroyDevice when use_softpinJose Maria Casanova Crespo1-0/+3
2018-06-28intel/fs: Build 32-wide FS shaders.Francisco Jerez1-11/+43
2018-06-28intel/anv,blorp,i965: Implement the SKL 16x MSAA SIMD32 workaroundJason Ekstrand2-2/+32
2018-06-28intel/fs: Add fields to wm_prog_data for SIMD32 dispatchJason Ekstrand4-1/+12
2018-06-28intel/fs: Fix nir_intrinsic_load_helper_invocation for SIMD32.Francisco Jerez1-5/+9
2018-06-28intel/fs: Fix fs_builder::sample_mask_reg() for 32-wide FS dispatch.Francisco Jerez1-3/+3
2018-06-28intel/fs: Fix Gen6+ interpolation setup for SIMD32Francisco Jerez1-56/+60
2018-06-28intel/fs: Get rid of MOV_DISPATCH_TO_FLAGSJason Ekstrand5-35/+8
2018-06-28intel/fs: Emit MOV_DISPATCH_TO_FLAGS once for the centroid workaroundJason Ekstrand2-50/+16
2018-06-28intel/fs: Generalize the unlit centroid workaroundFrancisco Jerez1-14/+8
2018-06-28intel/fs: Fix sample id setup for SIMD32.Francisco Jerez1-9/+25
2018-06-28intel/fs: Fix Gen7 compressed source region alignment restriction for SIMD32Francisco Jerez1-1/+7
2018-06-28intel/fs: Implement 32-wide FS payload setup on Gen6+Francisco Jerez1-67/+57
2018-06-28intel/fs: Extend thread payload layout to SIMD32Francisco Jerez3-22/+45
2018-06-28intel/fs: Wrap FS payload register look-up in a helper function.Francisco Jerez3-12/+23
2018-06-28intel/fs: Use fs_regs instead of brw_regs in the unlit centroid workaroundFrancisco Jerez1-12/+12
2018-06-28intel/fs: Simplify fs_visitor::emit_samplepos_setupFrancisco Jerez1-21/+7
2018-06-28i965: Add plumbing for shader time in 32-wide FS dispatch mode.Francisco Jerez4-3/+4
2018-06-28intel/fs: Disable opt_sampler_eot() in 32-wide dispatch.Francisco Jerez2-1/+6
2018-06-28intel/fs: Emit LINE+MAC for LINTERP with unaligned coordinatesJason Ekstrand2-10/+56
2018-06-28intel/fs: Mark LINTERP opcode as writing accumulator on platforms without PLNJason Ekstrand1-1/+2
2018-06-28intel/fs: Rework INTERPOLATE_AT_PER_SLOT_OFFSETFrancisco Jerez3-19/+9
2018-06-28intel/fs: Add the group to the flag subreg number on SNB and olderJason Ekstrand1-1/+7
2018-06-28intel/fs: Fix FB read header setup for SIMD32.Francisco Jerez1-4/+13
2018-06-28intel/fs: Fix logical FB write lowering for SIMD32Francisco Jerez1-5/+20
2018-06-28intel/fs: Fix FB write message control codegen for SIMD32.Francisco Jerez1-18/+34
2018-06-28intel/fs: Don't enable dual source blend if no outputs are writtenFrancisco Jerez1-1/+2
2018-06-28intel/fs: Fix codegen of FS_OPCODE_SET_SAMPLE_ID for SIMD32.Francisco Jerez1-11/+13
2018-06-28intel/eu: Fix pixel interpolator queries for SIMD32.Francisco Jerez1-1/+2
2018-06-28intel/fs: Disable SIMD32 dispatch for fragment shaders with discard.Francisco Jerez1-0/+2
2018-06-28intel/fs: Disable SIMD32 dispatch on Gen4-6 with control flowFrancisco Jerez1-0/+8
2018-06-28intel/fs: Split instructions low to high in lower_simd_widthJason Ekstrand1-2/+35
2018-06-28intel/fs: Rework KSP data to be SIMD width-basedJason Ekstrand3-47/+43
2018-06-28intel/compiler: Add and use helpers for working with KSP indicesJason Ekstrand3-32/+136
2018-06-28intel/fs: Remove program key argument from generator.Francisco Jerez7-10/+7