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2014-05-01gallivm: fix 2 leaks in disassembly codeRoland Scheidegger1-4/+5
don't leak the MCSubtargetInfo (not really big, was already fixed with llvm master) and TargetMachine (big). While this is only used for debugging the leak is large enough to get you into trouble in some cases. Tested with llvm 3.1 and master. Before (llvm 3.1), GALLIVM_DEBUG=asm glxgears: ==14152== LEAK SUMMARY: ==14152== definitely lost: 105,228 bytes in 20 blocks ==14152== indirectly lost: 347,252 bytes in 261 blocks ==14152== possibly lost: 866,625 bytes in 1,453 blocks ==14152== still reachable: 7,344,677 bytes in 6,494 blocks ==14152== suppressed: 0 bytes in 0 blocks After: ==13799== LEAK SUMMARY: ==13799== definitely lost: 3,108 bytes in 6 blocks ==13799== indirectly lost: 0 bytes in 0 blocks ==13799== possibly lost: 804,143 bytes in 1,429 blocks ==13799== still reachable: 7,314,267 bytes in 6,473 blocks ==13799== suppressed: 0 bytes in 0 blocks Reviewed-by: Brian Paul <brianp@vmware.com>
2014-04-29translate_sse: Use the correct buffer index in this fast path.Andreas Hartmetz1-1/+3
It is possible that there are multiple input buffers but only one is relevant for translation. Then there will be only a single translation group, which might need to source data from a buffer index != 0. Fixes wrong vertex shader inputs as observed while debugging with an application and driver combination that requires translation of a vertex attribute in a non-trivial set of attributes and input buffers. Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-04-29clover: Query drivers for max clock frequencyTom Stellard3-1/+8
Igor Gnatenko: v2: PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY instead of PIPE_COMPUTE_MAX_CLOCK_FREQUENCY Bruno Jiménez: v3: Drivers report clock in Mhz Signed-off-by: Igor Gnatenko <i.gnatenko.brain@gmail.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-04-29radeon/compute: Implement PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCYTom Stellard3-0/+13
Igor Gnatenko: v2: in define RADEON_INFO_MAX_SCLK use 0x1a instead of 0x19 (upstream changes) Bruno Jiménez: v3: Convert the frequency to MHz from kHz after getting it in 'do_winsys_init' Signed-off-by: Igor Gnatenko <i.gnatenko.brain@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2014-04-29gallium: Add PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCYTom Stellard2-1/+4
Bruno Jiménez: v2: Updated the docs v3: Remove trailing comma Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-04-29clover: Stub implementation of CL 1.2 sub-devices.EdB3-4/+66
The implementation is basically a NOP but it conforms with OpenCL 1.2. [ Francisco Jerez: Initialize property return buffer for CL_DEVICE_PARTITION_PROPERTIES, CL_DEVICE_PARTITION_TYPE, CL_DEVICE_PARTITION_AFFINITY_DOMAIN, and make the latter a scalar rather than a vector. Some clean-up and code style fixes. ] Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-04-29clover: Add clEnqueue{Marker, Barrier}WithWaitList.EdB2-7/+43
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-04-29clover: Align kernel argument sizes to nearest power of 2Jan Vesely1-7/+16
v2: use a new variable for aligned size add comment make both vars const only use the aligned value in argument constructors fix comment typo Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-04-29clover: Avoid warnings from references to deprecated CL 1.1 APIs.Francisco Jerez1-0/+2
Acked-by: Tom Stellard <thomas.stellard@amd.com>
2014-04-29clover: Update OpenCL headers to version 1.2 from Khronos.Francisco Jerez1-2/+6
The C++ headers are *not* updated because they rely on CL 1.2 APIs that we do not implement yet when the core CL 1.2 headers are present. Acked-by: Tom Stellard <thomas.stellard@amd.com>
2014-04-28nvc0/ir: offset appears to come before the Z refIlia Mirkin1-1/+3
Fixes textureGatherOffset when used with a shadow sampler. Also verified against blob compiler with textureLodOffset manually (no piglit tests for texture[Lod]Offset + shadow samplers). Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-04-28nv50/ir: change texture offsets to ValueRefs, allow nonconstIlia Mirkin8-20/+61
This allows us to have non-constant offsets for textureGatherOffset and textureGatherOffsets. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-04-28nvc0/ir: do constant folding of extbf/insbfIlia Mirkin1-1/+66
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-04-28nvc0/ir: add support for MUL_HI tgsi opcodesIlia Mirkin1-1/+12
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-04-28nvc0/ir: add support for new bitfield manipulation opcodesIlia Mirkin7-4/+127
This adds support for: IBFE, UBFE, BFI, LSB, IMSB, UMSB, BREV, POPC Which are all required for ARB_gs5 support. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-04-28tgsi: add tgsi_exec support for new bit manipulation opcodesIlia Mirkin1-0/+172
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-04-28gallium/util: add helpers for bitfield manipulationIlia Mirkin1-0/+31
Add bitwise reversing and signed MSB helpers for software implementation of the new TGSI opcodes. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-04-28gallium: add new opcodes for ARB_gs5 bit manipulation supportIlia Mirkin3-1/+93
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-04-28st/dri: cleanup dri extension handlingEmil Velikov2-25/+30
Explicitly set the version that is implemented, as that may differ from the one defined in dri_interface.h. Use designated initialisers and constify whereever possible. Note: __DRIimageExtension should not be made const as it's modified at runtime. This patch should have no side effects on compilers that do not support designated initialisers, as the existing code in dri/common already uses them. Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
2014-04-28util: Fix cross-compiles between endiannessesRichard Sandiford2-32/+46
The old python code used sys.is_big_endian to select between little-endian and big-endian formats, which meant that the build and host endiannesses needed to be the same. This patch instead generates both big- and little- endian layouts, using PIPE_ARCH_BIG_ENDIAN to select between them. Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com> Signed-off-by: José Fonseca <jfonseca@vmware.com>
2014-04-28util: Split out channel-parsing Python codeRichard Sandiford1-46/+50
Splits out the code that parses the channel list, so that we can have different lists for little and big endian. There is no change to the generated u_format_table.c. Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com> Signed-off-by: José Fonseca <jfonseca@vmware.com>
2014-04-28util: Split out channel-printing Python codeRichard Sandiford2-41/+69
Rather than iterate over format.channels and format.swizzles directly, use Python subfunctions that take the channel and swizzle lists as arguments. This allow the channel and swizzle lists to depend on endianness. There is no change to the generated u_format_table.c. Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com> Signed-off-by: José Fonseca <jfonseca@vmware.com>
2014-04-28util: Turn inv_swizzle into a global functionRichard Sandiford2-11/+11
With the big-endian changes, there can be two swizzle orders for each format. This patch turns Format.inv_swizzle() into a global function that takes the swizzle list as a parameter. There is no change to the generated u_format_table.c. Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com> Signed-off-by: José Fonseca <jfonseca@vmware.com>
2014-04-28util: Add more query methods to u_format_parse.FormatRichard Sandiford3-36/+51
The main aim is to reduce the number of places that access channels[0], swizzles[0] and swizzles[1] directly. There is no change to the generated u_format_table.c. Signed-off-by: Richard Sandiford <rsandifo@linux.vnet.ibm.com> Signed-off-by: José Fonseca <jfonseca@vmware.com>
2014-04-26nvc0/ir: fetch shadow value from proper place for TG4 cube arrayIlia Mirkin1-1/+4
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-04-26nvc0/ir: set gatherComp for non-shadow targetsIlia Mirkin1-0/+2
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-04-26nvc0/ir: set instance count based on the GS_INVOCATIONS propertyIlia Mirkin1-3/+1
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-04-26nvc0/ir: add support for INVOCATIONID system valueIlia Mirkin3-2/+1
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-04-26nvc0/ir: add support for SAMPLEMASK sysvalIlia Mirkin5-0/+8
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-04-26gallium: add GS_INVOCATIONS propertyIlia Mirkin3-1/+19
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-04-26gallium: add INVOCATIONID semanticIlia Mirkin3-2/+10
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-04-26nvc0: add support for PIPE_CAP_SAMPLE_SHADINGIlia Mirkin15-14/+131
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-04-26nv50: add support for PIPE_CAP_SAMPLE_SHADINGIlia Mirkin14-8/+107
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-04-26mesa/st: add support for ARB_sample_shadingIlia Mirkin5-0/+32
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-04-26gallium: add basic support for ARB_sample_shadingIlia Mirkin19-2/+48
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-04-25gallium/tests: conditionally include sw/dri winsysEmil Velikov1-1/+5
In all fairness we allow the gallium tests to be build with --disable-dri which will result in the approapriate winsys to not be build, thus the build will fail. ./configure --disable-dri --with-gallium-drivers=svga --enable-gallium-tests Cc: Brian Paul <brianp@vmware.com> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-04-25automake: cleanup pipe-loader handling when using sw/xlib winsysEmil Velikov4-4/+4
Rather than defining our own set of variables, use NEED_WINSYS_XLIB and based on it include the sw/xlib winsys. Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-04-25pipe-loader: conditionally build and use pipe_loader_sw_probe_driEmil Velikov2-0/+6
The function relies on the sw/dri winsys which is build only when --enable-dri is set. Fixes build issues with the following config ./configure --disable-dri --with-gallium-drivers=svga --enable-xa Issue can be reproduced with any hw gallium driver + st that uses the pipe-loader. Cc: Brian Paul <brianp@vmware.com> Reported-by: Brian Paul <brianp@vmware.com> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-04-25llvmpipe: fix clearing of individual color buffers in a fbRoland Scheidegger6-163/+190
GL (3.0) allows you to clear individual color buffers in a fb. In fact for fbs containing both int and float/normalized color buffers this is required (because the clearing values are otherwise undefined if applied to all buffers). The gallium interface was changed a while ago, but llvmpipe ignored it (hence doing such individual clears always resulted in clearing all buffers, plus some assorted asserts due to the mixed fbs). So change the clear command to indicate the buffer to be cleared. Also, because indicating the buffer to be cleared would have made lp_rast_arg_cmd larger which is unacceptable (we're trying to shrink it some day) allocate the clear value in the scene and just pass a pointer. There's several advantages and disadvantages here: + clearing individual buffers works (we could also actually bin such clears now if they'd come through clear_render_target() if the surface is in the current fb, though we didn't do this before for the single rb case and still don't try). + since there's one clear per rb, we do the format conversion in setup rather than per bin. Aside from the (drop in the ocean...) performance advantage this means that clearing to very small values (that is, denormal when converted to the format) should work for small float (fp16 etc.) formats, as the util code couldn't handle it correctly before (because cpu denorms are disabled when executing the bin commands, screwing up the magic conversion and flushing the values to 0, though this was not verified). - there's some overhead for traditional old-style clear-all MRT cases, since there's one rast clear command per rb instead of one for all rbs. This fixes https://bugs.freedesktop.org/show_bug.cgi?id=76976. v2: get rid of the ugly manual memcpy stuff and just use union util_color. This is 32 bytes instead of 16 but as the allocation is per scene we can live with those additional 16 bytes (and the additional 128 bytes in the setup context), which makes the code much more obvious. Suggested by Brian. Reviewed-by: Brian Paul <brianp@vmware.com>
2014-04-25gallium/util: use ui[4] instead of ui in union util_colorRoland Scheidegger11-38/+38
util_color often merely represents a collection of bytes, however it is inconvenient if those bytes can only be accessed as floats/doubles for int formats exceeding 32bits. (Note that since rgba8 formats use one uint, not 4 bytes, hence the byte and short member were left as is.)
2014-04-25llvmpipe: (trivial) use correct LP_MIN_VECTOR_ALIGN define for alignment.Roland Scheidegger1-1/+1
Currently it's the same value. Reviewed-by: Brian Paul <brianp@vmware.com>
2014-04-25r600g: fix hang on RV740 by using DX_RASTERIZATION_KILL instead of SX_MISCMarek Olšák5-7/+27
Changing SX_MISC hangs RV740. When we're at it, let's use DX_RASTERIZATION_KILL on all R700 and later chipsets. Cc: 10.0 10.1 mesa-stable@lists.freedesktop.org Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-04-25r600g: fix for an MSAA hang on RV770Marek Olšák3-1/+12
Cc: 10.0 10.1 mesa-stable@lists.freedesktop.org Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-04-25r600g: fix for broken CULL_FRONT behavior on R6xxMarek Olšák4-61/+64
Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-04-25r600g: fix for HTILE on R6xxMarek Olšák1-0/+6
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-04-25r600g: fix buffer copying on R600-R700Marek Olšák1-0/+6
This fixes broken rendering in DOTA 2. Cc: 10.0 10.1 mesa-stable@lists.freedesktop.org Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-04-25r600g: fix flushing on RV670, RS780, RS880 againMarek Olšák1-0/+9
Cc: 10.0 10.1 mesa-stable@lists.freedesktop.org Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-04-25r600g: fix MSAA resolve on R6xx when the destination is 1D-tiledMarek Olšák1-0/+6
Cc: 10.0 10.1 mesa-stable@lists.freedesktop.org Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-04-25r600g: disable async DMA on R700Marek Olšák1-1/+2
Cc: 10.0 10.1 mesa-stable@lists.freedesktop.org
2014-04-25r600g: fix edge flags and layered rendering on R600-R700Marek Olšák1-2/+4
We forgot to set these bits. Cc: 10.1 mesa-stable@lists.freedesktop.org Reviewed-by: Alex Deucher <alexander.deucher@amd.com>