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2024-03-22treewide: Replace usage of macro DEBUG with MESA_DEBUG when possibleYonggang Luo1-9/+9
This is achieved by the following steps: #ifndef DEBUG => #if !MESA_DEBUG defined(DEBUG) => MESA_DEBUG #ifdef DEBUG => #if MESA_DEBUG This is done by replace in vscode excludes docs,*.rs,addrlib,src/imgui,*.sh,src/intel/vulkan/grl/gpu These are safe because those files should keep DEBUG macro is already excluded; and not directly replace DEBUG, as we have some symbols around it. Use debug or NDEBUG instead of DEBUG in comments when proper This for reduce the usage of DEBUG, so it's easier migrating to MESA_DEBUG These are found when migrating DEBUG to MESA_DEBUG, these are all comment update, so it's safe Replace comment /* DEBUG */ and /* !DEBUG */ with proper /* MESA_DEBUG */ or /* !MESA_DEBUG */ manually DEBUG || !NDEBUG -> MESA_DEBUG || !NDEBUG !DEBUG && NDEBUG -> !(MESA_DEBUG || !NDEBUG) Replace the DEBUG present in comment with proper new MESA_DEBUG manually Signed-off-by: Yonggang Luo <luoyonggang@gmail.com> Acked-by: David Heidelberg <david.heidelberg@collabora.com> Reviewed-by: Eric Engestrom <eric@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28092>
2024-03-15winsys/amdgpu: remove tab spaceYogesh Mohan Marimuthu1-12/+10
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27968>
2024-03-15winsys/amdgpu: aws instead of ws for amdgpu_winsysYogesh Mohan Marimuthu1-172/+172
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27968>
2024-03-15winsys/amdgpu: rws instead of ws for radeon_winsysYogesh Mohan Marimuthu1-6/+6
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27968>
2024-03-15winsys/amdgpu: sws instead of ws for amdgpu_screen_winsysYogesh Mohan Marimuthu1-20/+20
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27968>
2024-03-15treewide: Replace the invalid usage #if DEBUG with #ifdef DEBUGYonggang Luo1-2/+2
This is done by find&replace and exclude the following folders in vscode docs,*.rs,addrlib,src/imgui,*.sh,src/intel/vulkan/grl/gpu This is a prepare step for re-working https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21946 These issues are found when to try switch DEBUG to MESA_DEBUG=0|1 in MR https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28092 Signed-off-by: Yonggang Luo <luoyonggang@gmail.com> Acked-by: David Heidelberg <david.heidelberg@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28083>
2024-02-17winsys/amdgpu: enable unlimited number of parallel queues for VCNMarek Olšák1-33/+59
This fixes a VCN performance regression introduced by the new BO fence tracking mechanism. VCN can have many queues. The current BO fence tracking mechanism only supports 1 queue per IP, and there is an interest to use all VCN queues via VAAPI. This introduces an alternative BO fence tracking mechanism that is only enabled for VCN, supports unlimited parallel queues, is similar to the previous system, can co-exist with the current queue system, and has no negative impact on CPU overhead as long as it's only used by VCN. Since we want an unlimited number of queues, we can't generate our own sequence numbers for those queues. Instead, each buffer will have a new field "alt_fence", which means an alternative fence. This fence is the last use of that buffer on any VCN queue. If any other queue wants to use that buffer, it has to insert alt_fence as a dependency, and replace alt_fence with the new submitted fence, so that it's always equal to the last use. Only VCN uses and updates alt_fence when an IB is submitted. Other IPs only use alt_fence as a fence dependency. alt_fence is NULL when VCN isn't used, so there is no negative impact on CPU overhead in that case. It uses a C++ template for amdgpu_cs_submit_ib due to different BO loop bodies between normal queues and VCN. Those loop bodies execute for every BO, so they shouldn't have extra code for alt_fence if the queue doesn't update it. Acked-and-Tested-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27627>
2024-02-07winsys/amdgpu: add real buffers of slab entries in the CS threadMarek Olšák1-0/+2
This removes the overhead from the driver thread and simplifies amdgpu_cs_add_buffer. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27408>
2024-01-10winsys/amdgpu: remove amdgpu_bo_sparse::gpu_address, use ↵Marek Olšák1-7/+10
amdgpu_va_get_start_addr Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26914>
2024-01-10winsys/amdgpu: remove amdgpu_bo_real::gpu_address, use amdgpu_va_get_start_addrMarek Olšák1-6/+4
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26914>
2024-01-06winsys/amdgpu: rename amdgpu_bo_real::lock to map_lockMarek Olšák1-7/+7
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26643>
2024-01-06winsys/amdgpu: rename amdgpu_bo_sparse::lock -> commit_lockMarek Olšák1-8/+8
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26643>
2024-01-06winsys/amdgpu: rename amdgpu_winsys_bo::bo -> bo_handleMarek Olšák1-19/+19
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26643>
2024-01-06winsys/amdgpu: rewrite BO fence tracking by adding a new queue fence systemMarek Olšák1-53/+36
This decreases the time spent in amdgpu_cs_submit_ib from 15.4% to 8.3% in VP2020/Catia1, which is a decrease of CPU load for that thread by 46%. Overall, it increases performance by a small number in CPU-bound benchmarks. The biggest improvement I have seen is VP2020/Catia2, where it increases FPS by 12%. It no longer stores pipe_fence_handle references inside amdgpu_winsys_bo. The idea is to have a global fixed list of queues (only 1 queue per IP for now) where each queue generates its own sequence numbers (generated by the winsys, not the kernel). Each queue also has a ring of fences. The sequence numbers are used as indices into the ring of fences, which is how sequence numbers are converted to fences. With that, each BO only has to keep a list of sequence numbers, 1 for each queue. The maximum number of queues is set to 6. Since the system can handle integer wraparounds of sequence numbers correctly, we only need 16-bit sequence numbers in BOs to have accurate busyness tracking. Thus, each BO uses only 12 bytes to represent all its fences for all queues. There is also a 1-byte bitmask saying which sequence numbers are initialized. amdgpu_winsys.h contains the complete description. It has several limitations that exist to minimize the memory footprint and updating of BO fences. Acked-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26643>
2024-01-06winsys/amdgpu: compute bo->unique_id at pb_slab_alloc, not at memory allocationMarek Olšák1-4/+1
We would compute the unique IDs for 1000 slab entries and then only use a few, wasting the IDs. Assign the IDs only when we actually need to return a new buffer. This decreases the number of collisions we get in amdgpu_lookup_buffer, and thus the number of times we have to search in the BO list. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26643>
2024-01-06winsys/amdgpu: allocate 1 amdgpu_bo_slab_entry per cache lineMarek Olšák1-2/+4
The structure size is exactly 64 bytes, so every entry occupies exactly 1 cache line. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26643>
2024-01-06r300,r600,radeonsi: switch to pb_buffer_leanMarek Olšák1-100/+100
to remove pb_buffer::vtbl from all buffer structures Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26643>
2024-01-06gallium/pb_cache: remove pb_cache_entry::bufferMarek Olšák1-4/+0
The buffer pointer is always at a constant offset from pb_cache_entry, so just pass the "offsetof" value to pb_cache and use that to get the pointer. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26643>
2024-01-06gallium/pb_cache: remove pb_cache_entry::mgrMarek Olšák1-1/+1
We can just pass it via functions. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26643>
2024-01-06gallium/pb_cache: switch to pb_buffer_leanMarek Olšák1-2/+2
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26643>
2024-01-06gallium/pb_buffer: define pb_buffer_lean without vtbl, inherit it by pb_bufferMarek Olšák1-68/+68
amdgpu doesn't need vtbl. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26643>
2024-01-06winsys/amdgpu: don't use gpu_address to compute slab entry offset in bo_mapMarek Olšák1-4/+12
use the code we have in amdgpu_bo_get_va Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26643>
2024-01-06winsys/amdgpu: remove va (gpu_address) from amdgpu_bo_slab_entryMarek Olšák1-13/+25
Keep it only in amdgpu_bo_real and amdgpu_bo_sparse. Slab entries can compute it from the slab BO and adding their entry index. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26643>
2024-01-06winsys/amdgpu: remove now-redundant amdgpu_bo_slab_entry::realMarek Olšák1-4/+2
The pb_slab pointer can be used to get the BO pointer because pb_slab is inside the BO structure now. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26643>
2024-01-06winsys/amdgpu: add amdgpu_bo_real_reusable slab for the backing bufferMarek Olšák1-51/+80
Add contents of amdgpu_bo_slab into it. This will allow removing the "real" pointer from amdgpu_bo_slab_entry because "(char*)entry.slab" is now pointing next to it. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26643>
2024-01-06winsys/amdgpu: don't layer slabs, use only 1 level of slabs, it improves perfMarek Olšák1-63/+32
This increases FPS in VP2020/Catia1 by 10-18%!!!!!!!!!!!!!!!!!!!!!!! I have no rational explanation for this. In the most extreme case, 8192 256B slab BOs (smallest size) are now allocated from a single 2MB slab. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26643>
2024-01-06winsys/amdgpu: stop using pb_buffer::vtblMarek Olšák1-23/+13
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26643>
2024-01-06winsys/amdgpu: rename to amdgpu_bo_slab to amdgpu_bo_slab_entryMarek Olšák1-10/+10
It's a slab entry. "Slab" is the whole buffer, which is AMDGPU_BO_REAL if we want to be precise. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26643>
2024-01-06iris,zink,winsys/amdgpu: remove unused/redundant slab->entry_sizeMarek Olšák1-4/+3
slab->base has the same field. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26643>
2024-01-06gallium/pb_slab: move group_index and entry_size from pb_slab_entry to pb_slabMarek Olšák1-5/+5
This removes 8 bytes from every slab entry, and thus amdgpu_bo_slab. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26643>
2023-12-13winsys/amdgpu: move lock from amdgpu_winsys_bo into sparse and real BOsMarek Olšák1-19/+16
The slab BO doesn't use it. Reviewed-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26547>
2023-12-13winsys/amdgpu: use inheritance for the slab BOMarek Olšák1-42/+39
Reviewed-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26547>
2023-12-13winsys/amdgpu: use inheritance for the sparse BOMarek Olšák1-75/+70
Reviewed-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26547>
2023-12-13winsys/amdgpu: use inheritance for the real BOMarek Olšák1-137/+130
add struct amdgpu_bo_real Reviewed-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26547>
2023-12-13winsys/amdgpu: use inheritance for the cache_entry BO fieldMarek Olšák1-14/+21
Add struct amdgpu_bo_real_reusable for it. This is the beginning of changing amdgpu_winsys_bo to use inheritance instead of a union. Reviewed-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26547>
2023-08-18radeonsi: modify algorithm of skipping holes of sparse boJulia Zhang1-22/+28
Modify current algorithm of skipping holes of sparse bo to cover the following using situations: 1. The whole sparse buffer is uncommitted. 2. More than one page that in the tail of sparse buffer are uncommitted. Signed-off-by: Julia Zhang <julia.zhang@amd.com> Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24535>
2023-08-18radeonsi: limit CP DMA to skip holes in sparse boFlora Cui1-0/+49
CP DMA on gfx9 can't handle the hole in sparse buffer. The fix skip sparse bo hole so that arb_sparse_buffer-buffer-data && arb_sparse_buffer-commit pass Signed-off-by: Flora Cui <flora.cui@amd.com> Signed-off-by: Julia Zhang <julia.zhang@amd.com> Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24535>
2023-08-10winsys/amdgpu: fix a race between import and destroyChia-I Wu1-10/+19
amdgpu_bo_destroy is called when the bo ref count reaches 0. But if the bo is on bo_export_table, amdgpu_bo_from_handle can race with amdgpu_bo_destroy and increments the bo ref count. When that happens, amdgpu_bo_destroy should bail. v2: - reorder amdgpu_bo_free and amdgpu_bo_unmap - fix an assert Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1) Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24526>
2023-06-06radeonsi: remove RADEON_FLAG_MALL_NOALLOC due to no useMarek Olšák1-4/+0
and we'll need to use that bit for something else in the future. Reviewed-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22833>
2023-06-05util: Replace all usage of PIPE_TIMEOUT_INFINITE with OS_TIMEOUT_INFINITEYonggang Luo1-2/+2
They are exactly the same, so it's safe to do the replace Also gen OS_TIMEOUT_INFINITE var with rusticl_mesa_bindings_rs by OS_ prefix and include "util/os_time.h" in rusticl/rusticl_mesa_bindings.h Reviewed-by: Jesse Natalie <jenatali@microsoft.com> Signed-off-by: Yonggang Luo <luoyonggang@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23401>
2023-05-24ac,radeonsi,winsyses: switch to SPDX-License-Identifier: MITMarek Olšák1-21/+1
excluding: aco, radv, addrlib Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Acked-by: David Heidelberg <david.heidelberg@collabora.com> Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23113>
2023-03-28amd/surface: rename metadata functionsPierre-Eric Pelloux-Prayer1-3/+3
Use more specific verbs to avoid confusion: set -> apply get -> compute Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21984>
2023-01-25winsys/amdgpu: use DMA_BUF_SET_NAME_B if availablePierre-Eric Pelloux-Prayer1-0/+13
Give a name to dma-buf. This name appears in /sys/kernel/debug/dma_buf/bufinfo and could be useful to debug dma-buf: Dma-buf Objects: size flags mode count exp_name ino name 00606208 00000002 00080007 00000003 drm 00192014 2321705-glxgears The name is only added to non-shared buffer, to avoid overwriting an existing name when exporting an imported buffer (otherwise all dma-buf will pretend to be created by XWayland). Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20728>
2022-10-31winsys/amdgpu: clamp up the alignment if zeroSunil Khatri1-1/+2
Zero alignment buffers is a valid alignment and is used for the cases when there is no special alignment enforced due to hardware requirement. Clamp up the buffer alignment of such buffers to gart_page_size. Screenshot app uses such buffers with zero alignment which is returned NULL by winsys and failed and hence failed to capture. Signed-off-by: Sunil Khatri <sunil.khatri@amd.com> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19314>
2022-08-25winsys/amdgpu: fix non-page-aligned sparse buffer creationQiang Yu1-1/+1
ARB_sparse_buffer does not require sparse buffer size to be page aligned. So we need to align it before VM ops as KMD will check whether it's aligned and return EINVAL if not. Fixes: 667da4eaed3 ("winsys/amdgpu: sparse buffer creation / destruction / commitment") Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7104 Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18206>
2022-08-09amdgpu/bo: update uses_secure_bos when importing buffersPierre-Eric Pelloux-Prayer1-0/+1
Fixes: 90b98c06493 ("amd/tmz: move uses_secure_bos to radeon_winsys") Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11449>
2022-06-22radeon: Support shared memory user pointers.Jason Volk1-1/+2
The RADEON_GEM_USERPTR_ANONONLY flag is hardcoded here which excludes shared memory pages. DRM is actually capable of supporting shared file- backed memory, but only if it's read-only. This mutability intent has to be conveyed through the stack, so a flags argument is added to the winsys regime to pass RADEON_FLAG_READ_ONLY. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16115>
2022-05-16radeonsi: use AMDGPU_VM_PAGE_NOALLOC to disable MALL (infinity cache)Marek Olšák1-0/+4
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16466>
2022-05-16radeonsi: use the new flag AMDGPU_GEM_CREATE_DISCARDABLEMarek Olšák1-1/+8
It forces the best placement (usually VRAM) and evictions discard the contents instead of copying. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16466>
2022-05-16winsys/amdgpu-radeon: clean up code related to heapsMarek Olšák1-18/+11
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16466>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-24 08:36:36 +0000