path: root/src/gallium/drivers/vc4
AgeCommit message (Expand)AuthorFilesLines
2017-01-16gallium: add PIPE_CAP_TGSI_FS_FBFETCHIlia Mirkin1-0/+1
2017-01-05vc4: Rewrite T image handling based on calling the LT handler.Eric Anholt1-34/+75
2017-01-05vc4: Move the utile_width/height functions to header inlines.Eric Anholt2-37/+36
2017-01-05vc4: Make the load/store utile functions static.Eric Anholt2-4/+2
2017-01-05vc4: Simplify the load/store utile functions.Eric Anholt1-10/+22
2017-01-05vc4: Reuse a list function to simplify bufmgr code.Eric Anholt1-11/+2
2017-01-05vc4: Flush the job early if we're referencing too many BOs.Eric Anholt3-0/+16
2017-01-05gallium: add PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELYMarek Olšák1-0/+1
2016-12-29nir: Rename convert_to_ssa lower_regs_to_ssaJason Ekstrand1-1/+1
2016-12-29vc4: Rework scheduling of thread switch to cut one more NOP.Eric Anholt1-46/+75
2016-12-29vc4: Fill thread switching delay slotsJonas Pfeil1-7/+38
2016-12-29vc4: Enable NIR-based loop unrolling.Eric Anholt1-0/+5
2016-12-12treewide: s/comparitor/comparator/Ilia Mirkin1-1/+1
2016-12-01gallium: support for native fence fd'sRob Clark1-0/+1
2016-11-30vc4: Avoid false scheduling dependencies for LOAD_IMMs.Eric Anholt2-0/+9
2016-11-30vc4: Try to schedule QIR instructions between writing to and reading math.Eric Anholt1-0/+22
2016-11-30vc4: Improve interleaving of texture coordinates vs results.Eric Anholt1-3/+3
2016-11-30vc4: Fix stray "." on no-op MUL packs.Eric Anholt1-6/+6
2016-11-30vc4: Allow merging instructions with SF set where the other writes NOP.Eric Anholt1-0/+1
2016-11-30vc4: In a loop break/continue, jump if everyone has taken the path.Eric Anholt1-10/+17
2016-11-30gallium: add PIPE_CAP_TGSI_CAN_READ_OUTPUTSNicolai Hähnle1-0/+1
2016-11-29vc4: Add a note for the future about texture latency calculation.Eric Anholt1-0/+20
2016-11-29vc4: Add support for coalescing ALU ops into tex_[srtb] MOVs.Eric Anholt4-29/+37
2016-11-29vc4: Restructure VPM write optimization into two passes.Eric Anholt1-18/+10
2016-11-29vc4: Make qir_for_each_inst_inorder() safe against removal.Eric Anholt1-1/+1
2016-11-29vc4: Split optimizing VPM writes from VPM reads.Eric Anholt5-51/+110
2016-11-29vc4: Restructure texture insts as ALU ops with tex_[strb] as the dst.Eric Anholt9-89/+194
2016-11-29vc4: Refactor qir_get_op_nsrc(enum qop) to qir_get_nsrc(struct qinst *).Eric Anholt17-36/+34
2016-11-29vc4: Replace the qinst src[] with a fixed-size array.Eric Anholt3-4/+2
2016-11-29vc4: Remove qir_inst4().Eric Anholt2-25/+0
2016-11-22vc4: Don't conditionalize the src1 mov of qir_SEL().Eric Anholt1-4/+2
2016-11-22vc4: Re-add R4 to the "any" register class.Eric Anholt1-0/+2
2016-11-22vc4: Disable MSAA rasterization when the job binning is single-sampled.Eric Anholt1-2/+13
2016-11-22vc4: Make sure we don't overflow texture input/output FIFOs when threaded.Eric Anholt1-2/+3
2016-11-22gallium: fix more occurences of u_hash.hMarek Olšák1-1/+1
2016-11-16vc4: Try compiling our FSes in multithreaded mode on new kernels.Eric Anholt5-2/+20
2016-11-16vc4: Add support for ETC1 textures if the kernel is new enough.Eric Anholt4-5/+18
2016-11-16vc4: Fix simulator mode missing-GETPARAM debug info.Eric Anholt1-1/+1
2016-11-16vc4: Fix resource leak in register allocation failure path.Mun Gwan-gyeong1-0/+2
2016-11-15gallium: add PIPE_SHADER_CAP_LOWER_IF_THRESHOLDMarek Olšák1-0/+1
2016-11-12vc4: Add simulator kernel validation for multithreaded fragment shaders.Jonas Pfeil3-5/+76
2016-11-12vc4: Mark threaded FSes as non-singlethread in the CL.Eric Anholt3-1/+6
2016-11-12vc4: Flag the last thread switch in the program as the last.Eric Anholt3-0/+34
2016-11-12vc4: Add THRSW nodes after each tex sample setup in multithreaded mode.Eric Anholt2-0/+49
2016-11-12vc4: Add some spec citations about texture fifo management.Eric Anholt1-5/+37
2016-11-12vc4: Use ra14/rb14 as the spilling registers.Eric Anholt2-8/+8
2016-11-12vc4: Add support for register allocation for threaded shaders.Eric Anholt3-20/+85
2016-11-12vc4: Split register class setup for physical files from accumulators.Eric Anholt1-17/+19
2016-11-12vc4: Use register allocator CLASS_BIT_R0_R3 to clean up CLASS_B.Eric Anholt1-4/+4
2016-11-12vc4: Add support for QPU scheduling of thread switch instructions.Eric Anholt1-2/+27