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path: root/src/gallium/drivers/vc4/vc4_qir_schedule.c
AgeCommit message (Expand)AuthorFilesLines
2017-03-08vc4: Fix register pressure cost estimates when a src appears twice.Eric Anholt1-3/+13
2016-11-30vc4: Try to schedule QIR instructions between writing to and reading math.Eric Anholt1-0/+22
2016-11-30vc4: Improve interleaving of texture coordinates vs results.Eric Anholt1-3/+3
2016-11-29vc4: Restructure texture insts as ALU ops with tex_[strb] as the dst.Eric Anholt1-23/+27
2016-11-29vc4: Refactor qir_get_op_nsrc(enum qop) to qir_get_nsrc(struct qinst *).Eric Anholt1-4/+4
2016-11-22vc4: Make sure we don't overflow texture input/output FIFOs when threaded.Eric Anholt1-2/+3
2016-11-12vc4: Add THRSW nodes after each tex sample setup in multithreaded mode.Eric Anholt1-0/+24
2016-11-12vc4: Add some spec citations about texture fifo management.Eric Anholt1-5/+37
2016-07-13vc4: Emit resets of the uniform stream at the starts of blocks.Eric Anholt1-0/+16
2016-07-12vc4: Define a QIR branch instructionEric Anholt1-0/+8
2016-07-12vc4: Make vc4_qir_schedule handle each block in the program.Eric Anholt1-14/+23
2016-07-12vc4: Create a basic block structure and move the instructions into it.Eric Anholt1-2/+3
2016-06-23Remove wrongly repeated words in commentsGiuseppe Bilotta1-1/+1
2016-05-30vc4: Fix doxygen warnings12.0-branchpointRhys Kidd1-2/+2
2016-04-08vc4: Allow TLB Z/color/stencil writes from any ALU operation in QIR.Eric Anholt1-11/+24
2016-04-08vc4: Add missing scheduling dependency for MS color writes.Eric Anholt1-0/+1
2016-03-16vc4: Move discard handling to the condition flag.Eric Anholt1-5/+0
2016-02-15vc4: Add missing braces in initializerRhys Kidd1-1/+1
2016-01-06vc4: Replace the SSA-style SEL operators with conditional MOVs.Eric Anholt1-4/+3
2015-12-18vc4: Do instruction scheduling on the QIR to hide texture fetch latency.Eric Anholt1-0/+619