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path: root/src/gallium/drivers/radeonsi/si_pipe.h
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15 hoursradeonsi: use ip_type in debug code instead of hardcoding GFXMarek Olšák1-2/+1
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
15 hoursradeonsi: make clear_render_target clear DCC directly instead of via ↵Marek Olšák1-0/+4
pipe->clear() This extracts the relevant parts from si_fast_clear. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
15 hoursradeonsi: enable fast FB clears for conditional renderingMarek Olšák1-1/+1
They use compute shaders, which always support the render condition. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
15 hoursradeonsi: don't flush CB and DB if there have been no draw callsMarek Olšák1-0/+4
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
15 hoursradeonsi: don't use si_get_flush_flags() for flushing imagesMarek Olšák1-0/+1
si_make_{CB/DB}_shader_coherent are more correct. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
15 hoursradeonsi: disable VRS flat shading for selected 8xMSAA and thick tiling casesMarek Olšák1-0/+1
for better slow clear performance Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
15 hoursradeonsi/gfx11: implement DCC clear to "single" for fast non-0/1 clearsMarek Olšák1-1/+8
If the clear color isn't 0 or 1, we used a slow clear. This adds a new DCC clear where the DCC buffer is cleared to a special value and the clear color is stored at the beginning of each 256B block in the image. It can be very fast, but it's not always faster than a slow clear. There is a heuristic that determines whether this new fast clear is better. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
15 hoursradeonsi: move blitter clear_render_target impl into si_gfx_clear_render_targetMarek Olšák1-0/+4
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
15 hoursradeonsi: move blitter resource_copy_region implementation to si_gfx_copy_imageMarek Olšák1-0/+4
for a new performance test. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
15 hoursradeonsi: use the same nir_lower_subgroups_options as RADVMarek Olšák1-0/+1
Some FREE calls are removed because nir_options is always NULL there. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28725>
12 daysnir: change "user_data_amd" sysval from 4 to 8 componentsMarek Olšák1-1/+1
so that we can pass more fast constants to compute shaders (without reading memory in the shader). Reviewed-by: Georg Lehmann <dadschoorse@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28606>
2024-03-30radeonsi: Remove tess bits from VS state.Timur Kristóf1-1/+1
These parts are not used anymore, therefore we no longer need to change the VS state when tessellation states change. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28425>
2024-03-30radeonsi: Delete TCS epilogs entirely.Timur Kristóf1-2/+1
Always emit the tessellation factor writes in the main shader, which is doable now that the necessary information is in the tcs_offchip_layout SGPR. This eliminates the need for TCS epilogs, so delete them entirely from RadeonSI. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28425>
2024-03-22radeonsi: implement the shader debug log from ac_nir_store_debug_log_amdMarek Olšák1-0/+3
This can be used to print values directly from shaders using ac_nir_store_debug_log_amd. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27952>
2024-03-11radeonsi: split RADEON_USAGE_NEEDS_IMPLICIT_SYNC into CB and DB flagsQiang Yu1-2/+6
it will be required in the future Signed-off-by: Qiang Yu <yuq825@gmail.com> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27943>
2024-03-11radeonsi: allocate only one set of tessellation rings per deviceMarek Olšák1-2/+5
Move them to si_screen. The "has_tessellation" context flag indicates that the screen has valid tess rings, so that we don't have to lock the mutex to check whether the rings are valid. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27943>
2024-02-07radeonsi,aco: remove the VS prologMarek Olšák1-1/+0
The upside is that this removes 600 lines of code. The downside is that if instance divisors are used, we will compile the VS on demand. Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27120>
2024-01-17radeonsi: rename *trivial_vs_prolog -> *trivial_vs_inputsMarek Olšák1-2/+2
This is a better name. Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26917>
2024-01-17radeonsi: split si_update_ngg_prim_state_sgpr into 2 functionsMarek Olšák1-8/+8
GS_STATE_PROVOKING_VTX_FIRST no longer depends on the primitive type, so we don't have to call it in si_set_rasterized_prim anymore. Reviewed-by: Qiang Yu <yuq825@gmail.com> Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26917>
2024-01-17radeonsi: change GS_STATE_PROVOKING_VTX_INDEX to 1 bit PROVOKING_VTX_FIRSTMarek Olšák1-3/+2
to save 1 bit for later Reviewed-by: Qiang Yu <yuq825@gmail.com> Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26917>
2024-01-14gallium: remove unbind_trailing_count from set_vertex_buffersMarek Olšák1-0/+1
It should implicitly unbind all bound buffers after "count". This also slightly simplies u_vbuf. This is a cleanup suggested by: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8142 Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> (asahi & panfrost) Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26309>
2024-01-06r300,r600,radeonsi: switch to pb_buffer_leanMarek Olšák1-6/+6
to remove pb_buffer::vtbl from all buffer structures Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26643>
2024-01-02radeonsi: convert "gfx11_create_sh_query_result_cs" shader to nirGanesh Belgur Ramachandra1-2/+0
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25972>
2024-01-02radeonsi: convert "create_query_result_cs" shader to nirGanesh Belgur Ramachandra1-1/+1
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25972>
2023-12-10gallium: add typedef pipe_draw_func matching the draw_vbo signature and use itMarek Olšák1-12/+6
We've copied the signature too many times already. This will also be used more. It intentionally deviates from the name by not including the "_vbo" part. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26619>
2023-12-09radeonsi: rework how guardband registers are updated to decrease overheadMarek Olšák1-6/+52
See the code comments. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26307>
2023-12-09radeonsi: convert rasterizer state to tracked registersMarek Olšák1-0/+1
Most of these registers don't change, so we should not set them when they don't. This reworks the rasterizer state to use a custom emit function and eliminate redundant register changes. This required merging the poly_offset state into the rasterizer state and change how the poly offset state is updated. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26307>
2023-12-09radeonsi: clean up how debug flags and shader profiles determine the wave sizeMarek Olšák1-1/+0
- remove DBG_W32_PS_DISCARD - just return the wave size instead of setting local variables dbg_wave_size and profile_wave_size Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26307>
2023-12-09radeonsi: rewrite si_get_total_colormask as si_any_colorbuffer_writtenMarek Olšák1-13/+7
The result is only used as bool. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26307>
2023-12-09radeonsi: rewrite how shader key bits dependent on current_rast_prim are updatedMarek Olšák1-1/+1
Don't set do_update_shaders every time current_rast_prim changes, which can be EVERY DRAW. Instead, just update the shader key bits and set do_update_shaders only if any bits are different. When we bind a new rasterizer state, do the same. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26307>
2023-12-09radeonsi: change the low-priority compiler queue to normal priorityMarek Olšák1-1/+1
I'm guessing that low priority could cause us to get optimized shaders later than we need. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26307>
2023-12-07radeonsi: use a compute shader to convert unsupported indices formatPierre-Eric Pelloux-Prayer1-0/+4
This commit replace the CPU-conversion of ubyte to ushort by a compute shader. The benefits are: * we don't need to sync anymore * we can allocate the index buffer in VRAM (no need to CPU map it) Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10195 Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26416>
2023-12-01ac: add an IB parser that gathers context rollsMarek Olšák1-0/+2
This is an important performance bottleneck analysis tool. Try it with radeonsi: AMD_ROLLS=filename app Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26349>
2023-11-17radeonsi: "get_blitter_vs" shader in nirGanesh Belgur Ramachandra1-1/+3
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25782>
2023-11-17radeonsi: "create_fmask_expand_cs" shader in nirGanesh Belgur Ramachandra1-1/+1
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25782>
2023-11-17radeonsi: "create_dma_compute" shader in nirGanesh Belgur Ramachandra1-1/+1
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25782>
2023-11-07radeonsi: move buffered_xx_regs into a substructureMarek Olšák1-4/+7
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26095>
2023-11-05radeonsi: various isolated cosmetic changesMarek Olšák1-1/+1
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26055>
2023-11-05radeonsi: remove AMD_DEBUG=nogfxMarek Olšák1-1/+0
it doesn't work - it uses the CDNA codepath for preamble, which surely hangs on non-CDNA Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26055>
2023-11-05radeonsi: inline si_screen_clear_bufferMarek Olšák1-2/+0
it has only one use Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26055>
2023-10-26radeonsi: move llvm compiler alloc/free into create/destroy funcntionQiang Yu1-1/+1
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25632>
2023-10-26radeonsi: move use_aco to si_screenQiang Yu1-0/+1
It's not per shader any more. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Qiang Yu <yuq825@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25632>
2023-10-19radeonsi: Add u_trace init code in radeonsiSaroj Kumar1-0/+8
Add u_trace initialization and callbacks in new files si_utrace.h/c Change si_context in si_pipe.h to add si_ds_queue and u_trace to collect traces. Add si_record_ts function in si_gfx_cs.c to add timestamp in command stream. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23664>
2023-10-19radeonsi: Add perfetto support in radeonsiSaroj Kumar1-0/+3
Add perfetto code in new files si_perfetto.h/cc which add tracepoint begin and end event and calls to the generated code from python si_tracepoints.py Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23664>
2023-10-05radeonsi: "clear_12bytes_buffer" shader in nirGanesh Belgur Ramachandra1-1/+1
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25221>
2023-10-05radeonsi: "clear_render_target_1d_array" shader in nirGanesh Belgur Ramachandra1-2/+1
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25221>
2023-10-05radeonsi: "clear_render_target" shader in nirGanesh Belgur Ramachandra1-1/+1
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25221>
2023-10-04radeonsi: upload shaders via a staging buffer so as not to map VRAM directlyMarek Olšák1-0/+1
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25494>
2023-10-04radeonsi: add another aux context for uploading shadersMarek Olšák1-5/+21
When the first auxiliary context is locked and wants to compile and upload a shader asynchronously, we need to use another auxiliary context in the compiler thread because the first one is locked at that point. This adds an array of auxiliary contexts into si_screen and changes how aux contexts are accessed. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25494>
2023-08-19radeonsi/gfx11: pass attribute ring addr via SGPR instead of memory for blitsMarek Olšák1-1/+1
This removes the scalar memory load from blit vertex shaders. Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24759>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-25 10:42:31 +0000