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2024-04-09r600: update licensing to SPDX headerDavid Heidelberg1-19/+2
Acked-by: Gert Wollny <gert.wollny@collabora.com> Signed-off-by: David Heidelberg <david@ixit.cz> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28395>
2023-10-31r600: Replace TGSI I/O semantics with shader_enumsVitaliy Triang3l Kuzmin1-35/+38
Removes the link-time dependency on tgsi_get_gl_varying_semantic from Gallium auxiliary. ps_prim_id_input linkage removed due to redundancy - the SPI SID is calculated for VARYING_SLOT_PRIMITIVE_ID on both sides. Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25695>
2023-10-31r600: Remove Gallium dependencies in r600_asmVitaliy Triang3l Kuzmin1-1/+2
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25695>
2023-10-01r600: Replace R600_BIG_ENDIAN with UTIL_ARCH_BIG_ENDIANVitaliy Triang3l Kuzmin1-2/+3
In particular, removes the dependency of r600_formats.h on r600_pipe.h so it can be shared between Gallium and Vulkan. Reviewed-by: Gert Wollny <gert.wollny@collabora.com> Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24513>
2023-08-18r600: better tracking for vertex buffer emissionMike Blumenkrantz1-3/+3
Fixes: 76725452 (gallium: move vertex stride to CSO) Reviewed-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24754>
2023-08-17r600: use correct cso pointer for fetch shaderGert Wollny1-1/+1
Fixes: 76725452 (gallium: move vertex stride to CSO) Related: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9567 Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24728>
2023-08-14gallium: move vertex stride to CSOMike Blumenkrantz1-1/+4
this simplifies code in most place and enables some optimizations in frontends Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24117>
2023-06-27treewide: Replace the usage of TRUE/FALSE with true/falseYonggang Luo1-14/+14
this is a separate patch as it's won't affect the code style Signed-off-by: Yonggang Luo <luoyonggang@gmail.com> Acked-by: David Heidelberg <david.heidelberg@collabora.com> Acked-by: Marek Olšák <marek.olsak@amd.com> Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23577>
2023-06-27treewide: replace usage of boolean to boolYonggang Luo1-2/+2
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com> Acked-by: David Heidelberg <david.heidelberg@collabora.com> Acked-by: Marek Olšák <marek.olsak@amd.com> Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23577>
2023-06-12r600: fix cayman_convert_border_color() swizzle behaviorPatrick Lerda1-9/+13
This change fixes a buffer overflow by implementing the special swizzles. This behavior is already available with evergreen_convert_border_color(). For instance, this issue is triggered on a cayman gpu with "piglit/bin/texwrap bordercolor -auto -fbo" or "piglit/bin/max-samplers -auto -fbo": ==5610==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x603000012d20 at pc 0x7fb798cb876f bp 0x7ffd78670460 sp 0x7ffd78670458 READ of size 4 at 0x603000012d20 thread T0 #0 0x7fb798cb876e in cayman_convert_border_color ../src/gallium/drivers/r600/evergreen_state.c:2444 #1 0x7fb798cb876e in evergreen_emit_sampler_states ../src/gallium/drivers/r600/evergreen_state.c:2539 #2 0x7fb7989e6cb2 in r600_emit_atom ../src/gallium/drivers/r600/r600_pipe.h:655 #3 0x7fb7989e6cb2 in r600_draw_vbo ../src/gallium/drivers/r600/r600_state_common.c:2333 #4 0x7fb7985082c7 in u_vbuf_draw_vbo ../src/gallium/auxiliary/util/u_vbuf.c:1497 #5 0x7fb796ef2eda in cso_draw_vbo ../src/gallium/auxiliary/cso_cache/cso_context.h:262 #6 0x7fb796ef2eda in st_draw_gallium_multimode ../src/mesa/state_tracker/st_draw.c:170 #7 0x7fb7970d9cfd in vbo_exec_vtx_flush ../src/mesa/vbo/vbo_exec_draw.c:341 #8 0x7fb7970d32d7 in vbo_exec_FlushVertices_internal ../src/mesa/vbo/vbo_exec_api.c:693 #9 0x7fb7970d32d7 in vbo_exec_FlushVertices ../src/mesa/vbo/vbo_exec_api.c:1193 #10 0x7fb7975f237c in enable_texture ../src/mesa/main/enable.c:337 Fixes: 923d635357f6 ("r600: fix some border color swizzles on CAYMAN") Signed-off-by: Patrick Lerda <patrick9876@free.fr> Reviewed-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23435>
2023-06-03compiler: Rename shader_prim to mesa_prim and replace all usage of ↵Yonggang Luo1-4/+4
pipe_prim_type with mesa_prim This is a prepare step to remove depends on p_defines.h in src/util/* This is done by: replace pipe_prim_type with mesa_prim replace shader_prim with mesa_prim replace PIPE_PRIM_MAX with MESA_PRIM_COUNT replace SHADER_PRIM_ with MESA_PRIM_ replace PIPE_PRIM_ with MESA_PRIM_ This patch only replace code only Signed-off-by: Yonggang Luo <luoyonggang@gmail.com> Acked-by: Marek Olšák <marek.olsak@amd.com> Acked-by: Jesse Natalie <jenatali@microsoft.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23369>
2023-05-01r600+sfn: Assign ps_conservative_z and switch to NIR definesGert Wollny1-3/+3
Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22778>
2023-04-17r600: fix refcnt imbalance related to evergreen_set_shader_images()Patrick Lerda1-1/+2
Indeed, the reference was overwritten. For instance, this issue is triggered with: "piglit/bin/shader_runner tests/spec/arb_shader_image_load_store/execution/write-to-rendered-image.shader_test -auto -fbo" while setting GALLIUM_REFCNT_LOG=refcnt.log. Fixes: a6b379284365 ("r600: add core pieces of image support.") Signed-off-by: Patrick Lerda <patrick9876@free.fr> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22394>
2023-04-17r600: Report multi-plane formats as unsupportedAndres Calderon Jaramillo1-0/+3
This is the analogous of https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9490 but for r600. Discoloration of NV12 video frames was observed in Chrome/ChromeOS and the problem was tracked down to the fact that Mesa was following the PIPE_FORMAT_R8_G8B8_420_UNORM/lower_yuv_external() path. The symptom is that (for an unknown reason) the YUV-to-RGB conversion is using the value of Y as the value of Y, U, and V. So, for example, if the input value is YUV = (50, 120, 130), then what actually gets converted to RGB is YUV = (50, 50, 50). Considering that PIPE_FORMAT_R8_G8B8_420_UNORM was introduced for freedreno (https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6693) and it is already being reported as unsupported for radeonsi, it's reasonable to assume that GPUs targeted by r600 don't support this path either. Note: I tested this patch with an AMD Palm device which follows the evergreen_is_format_supported() path. I did not have access to a device to test the r600_is_format_supported() path. v2: Changed >= 2 to > 1. Fixes: 826a10255f5 ("st/mesa: Add NV12 lowering to PIPE_FORMAT_R8_G8B8_420_UNORM") Tested-by: Andres Calderon Jaramillo <andrescj@chromium.org> Reviewed-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22511>
2023-04-13r600: fix typosHarri Nieminen1-2/+2
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22432>
2023-04-13r600: Alpha to coverage dithering on Evergreen+Vitaliy Triang3l Kuzmin1-7/+21
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22384>
2023-04-04r600: fix typo that could lead to a possible crashPatrick Lerda1-1/+1
For instance, with "piglit/bin/arb_shader_image_load_store-host-mem-barrier --quick -auto -fbo": ==18549==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x61200000a059 at pc 0x7f65d8937b80 bp 0x7fff6ed19a00 sp 0x7fff6ed199f8 READ of size 1 at 0x61200000a059 thread T0 #0 0x7f65d8937b7f in evergreen_set_shader_images ../src/gallium/drivers/r600/evergreen_state.c:4277 #1 0x7f65d6b471b8 in st_bind_images ../src/mesa/state_tracker/st_atom_image.c:172 #2 0x7f65d6b76b26 in st_validate_state ../src/mesa/state_tracker/st_util.h:129 #3 0x7f65d6b76b26 in prepare_draw ../src/mesa/state_tracker/st_draw.c:88 #4 0x7f65d6b77c8a in st_draw_gallium ../src/mesa/state_tracker/st_draw.c:141 #5 0x7f65d72698a2 in _mesa_draw_arrays ../src/mesa/main/draw.c:1202 Fixes: a6b379284365 ("r600: add core pieces of image support.") Signed-off-by: Patrick Lerda <patrick9876@free.fr> Reviewed-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22273>
2023-01-02r600: Fix early exit when setting SSBOsGert Wollny1-2/+2
Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20451>
2022-12-02r600: Use get_first_non_void_channel more oftenKonstantin Seurer1-10/+2
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18634>
2022-11-07r600: Fix some border color swizzles on EvergreenGert Wollny1-16/+47
Note: (u)int32 is broken on this hardware. Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19532>
2022-11-07r600: fix some border color swizzles on CAYMANGert Wollny1-5/+45
Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19532>
2022-07-27gallium/radeon: require radeon DRM 2.45.0 from April 2016Marek Olšák1-13/+4
This removes most non-radeonsi workarounds. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17411>
2022-05-13amd: change chip_class naming to "enum amd_gfx_level gfx_level"Marek Olšák1-27/+27
This aligns the naming with PAL. Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Acked-by: Pierre-Eric Pellou-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16469>
2022-05-02r600: Allow eight bit, three channel formats for vertex buffersGert Wollny1-2/+2
While using three component texture formats results in CTs failures, three component vertex attributes are fine, and not allowing them results in significant performance regressisons. Fixes: e41958e344cb4b15d01008140a1ee08817104334 r600: Disable eight bit three channel formats Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6399 v2: rename function to is_buffer_format_supported (Emma) Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Reviewed-by: Emma Anholt <emma@anholt.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16267>
2022-03-28r600: Update the PS state when MSAA-ness changes, too.Emma Anholt1-7/+12
Avoids a regression when enabling shader precompilation, where the precompile would happen with MSAA disabled (so no sample mask export) but we'd never catch up to the shader being rendered with MSAA. Doesn't fix any current testcases, though. Acked-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14427>
2021-10-29gallium/radeon: merge BO read/write usage flags with priority flagsMarek Olšák1-27/+26
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13478>
2021-10-29gallium/radeon: remove/merge some BO priorities and remove holesMarek Olšák1-1/+1
The upper bits will be used by RADEON_USAGE_* Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13478>
2021-08-21gallium: remove vertices_per_patch, add pipe_context::set_patch_verticesMarek Olšák1-3/+11
We would like draw-only display lists to have immutable draw info and this is the only GL non-draw state in pipe_draw_info (not counting view_mask). It also allows removing some code from draw_vbo for tessellation. Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12351>
2021-06-04r600: explicitly advertise index buffer format supportErik Faye-Lund1-0/+5
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11132>
2021-04-12ac/surface: use named "color and "zs" structures in unionsMarek Olšák1-2/+2
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>
2021-04-12ac/surface: change legacy_surf_level::offset to 32-bit offset_256B shifted by 8Marek Olšák1-12/+12
Images are always aligned to 256B (enforced by register and descriptor fields) and limited to 40-bit addresses. This saves some space. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10083>
2021-02-25r600: Fix typos.Vinson Lee1-2/+2
Signed-off-by: Vinson Lee <vlee@freedesktop.org> Reviewed-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8293>
2021-01-27gallium: add unbind_num_trailing_slots to set_shader_imagesMarek Olšák1-2/+14
Instead of calling this function again to unbind trailing slots, extend it to do it when images are being set. This reduces CPU overhead. Only st/mesa benefits. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8298>
2021-01-27gallium: add take_ownership param into set_constant_buffer to eliminate atomicsMarek Olšák1-7/+6
We often do this: pipe->set_constant_buffer(pipe, shader, slot, &cb); pipe_resource_reference(&cb->buffer, NULL); That results in atomic increment in set_constant_buffer followed by atomic decrement after set_constant_buffer. This new interface eliminates those atomics. For the case above, this should be used instead: pipe->set_constant_buffer(pipe, shader, slot, true, &cb); cb->buffer = NULL; // if cb is not a local variable, else do nothing AMD Zen benefits from this. The perf improvement is ~3% for Viewperf13/Catia. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8298>
2020-12-22gallium: inline pipe_depth_state to decrease DSA state size by 4 bytesMarek Olšák1-5/+5
Depth and alpha states are now packed together, interleaved somewhat. Reviewed-by: Eric Anholt <eric@anholt.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7940>
2020-12-22gallium: inline pipe_alpha_state to enable better DSA bitfield packingMarek Olšák1-3/+3
pipe_alpha_state and pipe_depth_state will be packed together because they have only a few bitfields each. This will eventually remove 4 bytes of padding in pipe_depth_stencil_alpha_state. Reviewed-by: Eric Anholt <eric@anholt.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7940>
2020-12-05r300,r600,radeonsi: inline struct radeon_cmdbuf to remove dereferencesMarek Olšák1-26/+26
It's straightforward except that the amdgpu winsys had to be cleaned up to allow this. radeon_cmdbuf is inlined and optionally the winsys can save the pointer to it. radeon_cmdbuf::priv points to the winsys cs structure. Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7907>
2020-05-24r600: Use TRUNC_COORD on samplersChristopher Egert1-0/+3
As per d573d1d82524b8a2e5f56938069cabc0f0176a0e the same should be done here. It seems like TRUNCATE_COORD not available on r600, so this is limited to evergreen. Reviewed-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5078>
2020-05-18r600: enable TEXCOORD semantic for TGSI.Dave Airlie1-11/+10
This should make intergrating with NIR easier Reviewed-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5083>
2019-10-28util: remove LIST_ADDTAIL macroTimothy Arceri1-1/+1
Just use the inlined function directly. The macro was replaced with the function in ebe304fa540f. Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2019-10-07gallium: add PIPE_RESOURCE_FLAG_SINGLE_THREAD_USE to skip util_range lockMarek Olšák1-1/+1
u_upload_mgr sets it, so that util_range_add can skip the lock. The time spent in tc_transfer_flush_region decreases from 0.8% to 0.2% in torcs on radeonsi. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-04r600: Fix interpolateAtCentroidGert Wollny1-0/+6
If the instruction interpolateAtCentroid is used the extra interpolator must also be enabled in the state. Fixes: fs-interpolateatcentroid-block Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-07-22gallium: switch boolean -> bool at the interface definitionsIlia Mirkin1-9/+9
This is a relatively minimal change to adjust all the gallium interfaces to use bool instead of boolean. I tried to avoid making unrelated changes inside of drivers to flip boolean -> bool to reduce the risk of regressions (the compiler will much more easily allow "dirty" values inside a char-based boolean than a C99 _Bool). This has been build-tested on amd64 with: Gallium drivers: nouveau r300 r600 radeonsi freedreno swrast etnaviv v3d vc4 i915 svga virgl swr panfrost iris lima kmsro Gallium st: mesa xa xvmc xvmc vdpau va Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-04-04gallium: add writable_bitmask parameter into set_shader_buffersMarek Olšák1-1/+2
to indicate write usage per buffer. This is just a hint (it will be used by radeonsi). Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-09-06gallium: enable GL_AMD_depth_clamp_separate on r600, radeonsiMarek Olšák1-1/+1
2018-09-06gallium: split depth_clip into depth_clip_near & depth_clip_farMarek Olšák1-2/+2
for AMD_depth_clamp_separate.
2018-08-21r600/eg: rework atomic counter emission with flushesDave Airlie1-15/+23
With the current code, we didn't do the space checks prior to atomic counter setup emission, but we also didn't add atomic counters to the space check so we could get a flush later as well. These flushes would be bad, and lead to problems with parallel tests. We have to ensure the atomic counter copy in, draw emits and counter copy out are kept in the same command submission unit. This reworks the code to drop some useless masks, make the counting separate to the emits, and make the space checker handle atomic counter space. [airlied: want this in 18.2] Fixes: 06993e4ee (r600: add support for hw atomic counters. (v3))
2018-07-31gallium: add storage_sample_count parameter into is_format_supportedMarek Olšák1-0/+4
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-07-25r600: Scale integer valued texture border colors to float (v2)Gert Wollny1-1/+44
It seems the hardware always expects floating point border color values [0,1] for unsigned, and [-1,1] for signed texture component, regardless of pixel type, but the border colors are passed according to texture component type. Hence, before submitting the border color, convert and scale it these ranges accordingly. This doesn't seem to work for textures with 32 bit integer components though, here, it seems that the border color is always set to zero, regardless of the BORDER_COLOR_TYPE state set in Q_TEX_SAMPLER_WORD0_0. v2: Simplyfy logic as suggested by Roland Schneidegger Fixes: dEQP-GLES31.functional.texture.border_clamp.formats.compressed* dEQP-GLES31.functional.texture.border_clamp.formats.r* (non 32 bit integer) dEQP-GLES31.functional.texture.border_clamp.per_axis_wrap_mode.texture_2d* and a number of piglits out of piglit run gpu -t texture -t gather -t formats Signed-off-by: Gert Wollny <gw.fossdev@gmail.com> Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2018-07-17r600g: some -Wsign-compare fixesKonstantin Kharlamov1-3/+3
Signed-off-by: Konstantin Kharlamov <Hi-Angel@yandex.ru> Signed-off-by: Marek Olšák <marek.olsak@amd.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-24 15:16:22 +0000