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path: root/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
AgeCommit message (Expand)AuthorFilesLines
2021-02-04nvc0/ir: Initialize SchedDataCalculator members in constructor.Vinson Lee1-1/+2
2021-01-21nvc0/ir: add fixup to deal with interpolateAtSample with non-MSAAIlia Mirkin1-3/+12
2020-08-25nv50/ir: Add nv50_ir_prog_info_out serialize and deserializeMark Menzynski1-7/+7
2018-07-07nvc0/ir: use the combined tid special registerRhys Perry1-0/+1
2018-04-24nvc0/ir: all short immediates are sign-extended, adjust LIMM testIlia Mirkin1-4/+8
2018-03-29nvc0/ir: fix emiting NOTs with predicatesKarol Herbst1-0/+2
2017-08-09nv50/ir: fix ConstantFolding with saturationKarol Herbst1-0/+1
2017-04-13nvc0/ir: Add SV_LANEMASK_* system values.Boyan Ding1-0/+5
2017-04-13nvc0/ir: Allow 0/1 immediate value as source of OP_VOTEBoyan Ding1-4/+20
2017-04-13nvc0/ir: Emit OP_SHFLBoyan Ding1-0/+53
2017-04-13nvc0/ir: Properly handle a "split form" of predicate destinationBoyan Ding1-2/+13
2017-02-09nvc0/ir: make it possible to have the flags def in def0Ilia Mirkin1-6/+8
2017-02-09nvc0/ir: fix SET and SLCT emissionIlia Mirkin1-0/+2
2017-02-09nvc0/ir: add support for emitting partial min/max ops for int64Ilia Mirkin1-1/+6
2017-01-15nvc0/ir: emit FMZ flag when requested on FFMAIlia Mirkin1-0/+4
2016-10-27nvc0/ir: fix emission of IMAD with NEG modifiersSamuel Pitoiset1-1/+1
2016-10-26nvc0/ir: fix emission of SHLADD with NEG modifiersSamuel Pitoiset1-1/+1
2016-10-22nvc0/ir: remove outdated comment about SHLADDSamuel Pitoiset1-1/+0
2016-09-29nvc0/ir: add emission for SHLADDSamuel Pitoiset1-0/+43
2016-09-17nvc0/ir: fix subops for IMADSamuel Pitoiset1-4/+6
2016-08-30nv50/ir: always emit the NDV bit for OP_QUADOPSamuel Pitoiset1-4/+1
2016-07-24nvc0/ir: fix up an assertion in emitUADD()Samuel Pitoiset1-4/+3
2016-06-06nvc0: add support for VOTE tgsi opcodesIlia Mirkin1-4/+19
2016-05-30nvc0/ir: fix spilling predicates to registersIlia Mirkin1-0/+4
2016-05-30nvc0/ir: fix emission of predicate spill to registerIlia Mirkin1-1/+2
2016-05-26nvc0/ir: handle a load's reg result not being used for locked variantsIlia Mirkin1-6/+20
2016-05-21nvc0/ir: add emission for SULDB and SUSTxSamuel Pitoiset1-2/+44
2016-05-21nvc0/ir: add emission for OP_SULEASamuel Pitoiset1-0/+58
2016-05-11nvc0: fix gl_SampleMaskIn computationIlia Mirkin1-0/+14
2016-05-11nv50/ir: generalize interp fixups to be able to fixup anythingIlia Mirkin1-4/+3
2016-04-26nvc0/ir: fix wrong emission of (a OP b) OP cSamuel Pitoiset1-2/+2
2016-04-01nvc0/ir: fix wrong pred emission for ld lock on GK104Samuel Pitoiset1-1/+4
2016-03-07nvc0/ir: make sure that thread count immediate for BAR fitSamuel Pitoiset1-0/+1
2016-02-28nv50/ir: emit VOTE instructionSamuel Pitoiset1-0/+23
2016-02-22nvc0/ir: add missing emission of locked load predicateSamuel Pitoiset1-0/+7
2016-02-22nvc0/ir: add ld lock/st unlock emission on GK104Samuel Pitoiset1-10/+25
2016-02-22nv50/ir: restore OP_SELP to be a regular instructionSamuel Pitoiset1-4/+4
2016-02-21nv50/ir: make OP_SELP a compare instructionSamuel Pitoiset1-4/+9
2016-02-21nv50/ir: add lock/unlock subops for load/storeSamuel Pitoiset1-2/+14
2016-02-16nv50/ir: fix quadop emission in the presence of predicationIlia Mirkin1-1/+1
2016-02-05nvc0/ir: fix converting between predicate and gprIlia Mirkin1-1/+7
2016-01-29nvc0/ir: fix atomic compare-and-swap argumentsIlia Mirkin1-2/+4
2016-01-03nvc0/ir: add support for PK2H/UP2HIlia Mirkin1-1/+4
2015-11-29nv50/ir: always display the opcode number for unknown instructionsSamuel Pitoiset1-1/+1
2015-11-18nvc0/ir: actually emit AFETCH on keplerIlia Mirkin1-0/+3
2015-11-12nvc0/ir: add support for TGSI_SEMANTIC_HELPER_INVOCATIONIlia Mirkin1-0/+1
2015-11-06nvc0/ir: Add support for double immediatesHans de Goede1-0/+8
2015-10-29nvc0: do upload-time fixups for interpolation parametersIlia Mirkin1-2/+28
2015-08-20nvc0/ir: detect i2f/i2i which operate on specific bytes/wordsIlia Mirkin1-0/+4
2015-08-17gk110/ir: fix sched calculator to consider all registers in the ISAIlia Mirkin1-7/+10