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path: root/include/pci_ids/i965_pci_ids.h
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2014-07-03i965: Include marketing names for Broadwell GPUs.Kenneth Graunke1-18/+18
Intel would like us to include the marketing names. Developers additionally want "Broadwell GT1/2/3" because it makes it easier to identify what hardware users have when they request assistance or report issues. Including both makes it easy for everyone to map between the names. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Cc: "10.2" <mesa-stable@lists.freedesktop.org> (cherry picked from commit 05126b9bb5763ab6a7418719e1ef2d660cc3c272)
2014-03-28i965: Add Cherryview support.Kenneth Graunke1-0/+4
Based on a patch by Ville Syrjälä. As usual, these are placeholder values; actual values will come later. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2014-02-20i965: Enable Broadwell support.Kenneth Graunke1-2/+0
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2014-01-31i965: Add (disabled) Broadwell PCI IDs.Kenneth Graunke1-0/+20
This puts the PCI IDs in place so it's easy to enable support. However, it doesn't actually enable support since it's very preliminary still, and a few crucial pieces (such as BLORP) are still missing. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Eric Anholt <eric@anholt.net>
2013-10-13i965: Add the family name to the PCI ID table.Kenneth Graunke1-93/+93
I removed this a while ago, since we never used it, but I'm finally resurrecting the idea in the next commits. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-10-13i965: Remove #define name from PCI ID table.Kenneth Graunke1-93/+93
Nothing uses the #define name, and it's not terribly useful - the numerical ID serves the same purpose. The only thing we could really do with it is generate slightly prettier preprocessed code. But who looks at that? Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-06-06intel: Use the CHIPSET macro in the PCI ID tables for the device name.Kenneth Graunke1-93/+93
Putting the human readable device names directly in the PCI ID list consolidates things in one place. It also makes it easy to customize the name on a per-PCI ID basis without a huge code explosion. Based on a patch by Kristian Høgsberg. v2: Fix 830M/845G names and #undef CHIPSET (caught by Emit Velikov). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-06-06intel: Remove 'misc' parameter from CHIPSET macro in PCI ID tables.Kenneth Graunke1-93/+93
This has never actually been used for anything. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
2013-06-05i965: Adding more reserved PCI IDs for Haswell.Rodrigo Vivi1-0/+24
At DDX commit Chris mentioned the tendency we have of finding out more PCI IDs only when users report. So Let's add all new reserved Haswell IDs. NOTE: This is a candidate for stable branches. Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=63701 Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-09i965: make GT3 machines work as GT3 instead of GT2Paulo Zanoni1-12/+12
We were not allowed to say the "GT3" name, but we really needed to have the PCI IDs because too many people had such machines, so we had to make the GT3 machines work as GT2. Let's just say that GT2_PLUS was a short for GT2_PLUS_1 :) NOTE: This is a candidate for stable branches. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-04-16i965: Enable the Bay Trail platform.Kenneth Graunke1-0/+5
This patch adds PCI IDs for Bay Trail (sometimes called Valley View). As far as the 3D driver is concerned, it's very similar to Ivybridge, so the existing code should work just fine. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2013-03-03i965: Fix Crystal Well PCI IDs.Kenneth Graunke1-9/+9
The second digit was off by one, which meant we accidentally treated GTn as GT(n-1). This also meant no support for GT1 at all. NOTE: This is a candidate for stable branches. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2012-08-07i965: add more Haswell PCI IDsPaulo Zanoni1-1/+32
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-04-01intel: add PCI IDs for Ivy Bridge GT2 server variantEugeni Dodonov1-0/+1
Those IDs are used by Bromolow. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
2012-03-30intel: Add some PCI IDs for Haswell.Kenneth Graunke1-0/+5
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2011-06-07Add intel pci id listsBenjamin Franzke1-0/+27
Reviewed-by: Alex Deucher <alexdeucher@gmail.com>