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AgeCommit message (Expand)AuthorFilesLines
31 hoursiris: Apply the flushes when switching pipelines.Rafael Antognolli1-12/+4
6 daysiris: Set MOCS for constant packets on Gen12+Kenneth Graunke1-0/+7
9 daysintel/gen12: Take into account opcode when decoding SWSBCaio Marcelo de Oliveira Filho2-3/+7
13 daysintel/fs/gen12: Workaround data coherency issues due to broken NoMask control...Francisco Jerez1-34/+100
13 daysintel/fs/gen12: Fixup/simplify SWSB annotations of SIMD32 scratch writes.Francisco Jerez1-7/+3
13 daysintel/fs/gen12: Workaround unwanted SEND execution due to broken NoMask contr...Francisco Jerez2-0/+150
2020-02-13intel/isl: Switch to R8_UNORM format for compatiblitySagar Ghuge1-0/+9
2020-02-05anv: implement gen12 post sync pipe control workaroundLionel Landwerlin1-1/+5
2020-02-05anv: implement gen9 post sync pipe control workaroundLionel Landwerlin3-0/+39
2020-02-05iris: implement gen12 post sync pipe control workaroundLionel Landwerlin1-1/+4
2020-01-31intel/gen12+: Set way_size_per_bank to 4Anuj Phogat1-1/+1
2020-01-31intel/gen12+: Reserve 4KB of URB space per bank for Compute EngineAnuj Phogat1-1/+19
2020-01-31intel/disasm: SEND has two sources on Gen12+Jason Ekstrand1-2/+4
2020-01-30intel/blorp: Always emit URB config on Gen7+Jason Ekstrand4-46/+68
2020-01-30anv,iris: Set 3DSTATE_SF::DerefBlockSize to per-poly on Gen12+Jason Ekstrand3-1/+13
2020-01-30genxml: Add a new 3DSTATE_SF field on gen12Jason Ekstrand1-0/+5
2020-01-29anv/block_pool: Ensure allocations have contiguous mapsJason Ekstrand5-15/+32
2020-01-28anv: Emit CS Stall before Instruction Cache flush for gen12 WAJordan Justen1-0/+6
2020-01-28iris: Emit CS Stall before Instruction Cache flush for gen12 WAJordan Justen1-0/+12
2020-01-28intel/mi_builder: Force write completion on Gen12+Jason Ekstrand1-0/+3
2020-01-28intel/blorp: Handle bit-casting UNORM and BGRA formatsJason Ekstrand1-37/+34
2020-01-26isl: add gen12 comment about CCS for linear tilingLionel Landwerlin1-0/+10
2020-01-26isl: drop CCS row pitch requirement for linear surfacesLionel Landwerlin1-15/+21
2020-01-26intel: Implement Gen12 workaround for array textures of size 1Lionel Landwerlin6-1/+151
2020-01-24intel/isl: Add a hack for the Gen12 A0 texture buffer bugJason Ekstrand1-0/+19
2020-01-24intel/fs: Don't unnecessarily fall back to indirect sends on Gen12Jason Ekstrand1-3/+4
2020-01-23anv/iris: warn gen12 3DSTATE_HS restrictionLionel Landwerlin2-0/+21
2020-01-23intel: Fix aux map alignments on 32-bit builds.Kenneth Graunke2-5/+5
2020-01-20isl/gen12: add reminder comment about missing WA with 3D surfacesTapani Pälli1-0/+13
2020-01-16anv: set depth stall enabled when depth flush enabled on gen12Tapani Pälli2-0/+19
2020-01-16iris: set depth stall enabled when depth flush enabled on gen12Tapani Pälli1-0/+9
2020-01-16genxml: add new Gen11+ PIPE_CONTROL fieldLionel Landwerlin2-0/+2
2020-01-15anv: fix pipeline switch back for non pipelined statesLionel Landwerlin1-13/+8
2020-01-14anv: Implement Gen12 workaround for non pipelined stateLionel Landwerlin1-0/+27
2020-01-14iris: Implement Gen12 workaround for non pipelined stateLionel Landwerlin1-0/+39
2019-12-17anv/gen12: Temporarily disable VK_KHR_buffer_device_address (and EXT)Caio Marcelo de Oliveira Filho1-2/+4
2019-12-13iris: Implement WA for push constants.Rafael Antognolli1-1/+12
2019-12-11intel: add mi_builder_test for gen12Eric Engestrom1-1/+1
2019-12-10anv: fix incorrect VMA alignment for CCS main surfacesLionel Landwerlin1-3/+14
2019-12-10anv: fix missing gen12 handlingLionel Landwerlin1-0/+3
2019-12-04intel/compiler: Fix 'comparison is always true' warningIan Romanick1-2/+2
2019-12-04anv: Use 3DSTATE_CONSTANT_ALL when possible.Rafael Antognolli1-3/+90
2019-12-04anv: Add get_push_range_address() helper.Rafael Antognolli1-59/+70
2019-12-04iris: Use 3DSTATE_CONSTANT_ALL when possible.Rafael Antognolli2-2/+76
2019-12-02iris: Allow max dynamic pool size of 2GB for gen12Jordan Justen1-1/+9
2019-10-30intel/dev: set default num_eu_per_subslice on gen12Lionel Landwerlin1-1/+2
2019-10-30docs/relnotes/new_features.txt: Add note about gen12 support19.3-branchpointJordan Justen1-0/+1
2019-10-30intel/eu/validate/gen12: Add TGL to eu_validate tests.Jordan Justen1-0/+9
2019-10-30intel/genxml: Add gen12 tile cache flush bitJordan Justen1-0/+1
2019-10-30iris: Align fast clear color state buffer to a page.Rafael Antognolli1-0/+5