summaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
23 hoursradeonsi/ci: update vangogh expectations after piglit uprevEric Engestrom1-78/+0
Fixes: ec45e8294cd39735d238 ("Uprev Piglit to f7ece74a107a2f99b2f494d978c84f8d51faa703") Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28852>
6 daysradeonsi: Adds return on failure to get plane infoSurafel Assefa1-4/+6
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27456>
10 daysnir: add nir_intrinsic_optimization_barrier_sgpr_amdMarek Olšák3-1/+9
for radeonsi Reviewed-by: Georg Lehmann <dadschoorse@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28606>
11 dayszink: enable opt_varyings with ZINK_DEBUG=iooptMike Blumenkrantz3-0/+157
uses copied instruction costs from radeonsi for AMD, need info for other platforms... Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28580>
11 daysradeonsi/uvd_enc: update to use correct padding sizenyanmisaka2-4/+4
Update padding size calculation to use cropping. Original method could result in 0 padding, which generated unnessary noise in the encoding result. Cc: mesa-stable Fixes: mesa/mesa#9196 Signed-off-by: nyanmisaka <nst799610810@gmail.com> Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28369>
12 daysfrontends/va: Only export one handle for contiguous planesHannes Mann1-23/+41
If the driver stores all planes contiguously in memory, only one BO needs to be exported from vaExportSurfaceHandle. This is required for Chromium's VaapiVideoDecoder to work on radeonsi and r600. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26165>
13 daysradeonsi/vpe: add support for p010Peyton Lee1-6/+42
add support for p010, correct the settings of format and buffer pitch. Signed-off-by: Peyton Lee <peytolee@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28518>
2024-04-02radv: Reuse TCS offchip layout between TCS and TES.Timur Kristóf5-41/+18
Using the same SGPR bitfield in TCS and TES will simplify driver code and make RADV consistent with RadeonSI. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28490>
2024-04-02radv: Change number of patches in TCS offchip layout to match RadeonSI.Timur Kristóf4-7/+9
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28490>
2024-04-02radv: Change input patch size in TCS offchip layout to match RadeonSI.Timur Kristóf4-6/+7
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28490>
2024-04-01radeonsi/vcn: use num_instances from radeon_infoSathishkumar S1-3/+3
num_instances is used to track ip count not num_queues. Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Acked-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28252>
2024-03-30radeonsi: Use one more bit for number of patches in TCS offchip layout.Timur Kristóf3-19/+11
There was 1 more bit left, may as well use it for something. In the future, this may allow increasing the maximum number of patches per workgroup. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28425>
2024-03-30radeonsi: Remove tess bits from VS state.Timur Kristóf4-26/+5
These parts are not used anymore, therefore we no longer need to change the VS state when tessellation states change. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28425>
2024-03-30radeonsi: Add number of VS outputs to TCS output layout.Timur Kristóf3-9/+17
Use tcs_offchip_layout instead of VS state to determine the number of LS outputs. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28425>
2024-03-30aco: Delete all TCS epilog code.Timur Kristóf5-348/+1
Now that neither RADV nor RadeonSI uses TCS epilogs, we don't need to keep the code to compile them in ACO either. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28425>
2024-03-30radeonsi: Delete TCS epilogs entirely.Timur Kristóf9-610/+5
Always emit the tessellation factor writes in the main shader, which is doable now that the necessary information is in the tcs_offchip_layout SGPR. This eliminates the need for TCS epilogs, so delete them entirely from RadeonSI. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28425>
2024-03-30radeonsi: Implement dynamic TCS intrinsics for non-monolithic shaders.Timur Kristóf3-3/+17
Put the primitive mode and whether TES reads tess factors into the tcs_offchip_layout SGPR, so they can be used by the main shader instead of needing the epilog. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28425>
2024-03-30radeonsi: Put HS output count in TCS offchip layout, not patch data offset.Timur Kristóf4-9/+34
The intention is to free up enough bits in tcs_offchip_layout so that it can contain information for more dynamic states. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28425>
2024-03-30ac/llvm, radeonsi: Handle tess_rel_patch_id in common code.Timur Kristóf2-4/+13
We'll need to clean this up later, but for now it's better to have it in common code than in RadeonSI. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28425>
2024-03-28radv, aco: Remove the code that jumped to RADV's TCS epilogs.Timur Kristóf3-87/+2
The actual TCS epilog selection code is kept unchanged for now, we'll delete it when RadeonSI also gets rid of TCS epilogs. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28408>
2024-03-28radeonsi: Implement new intrinsics for monolithic shaders.Timur Kristóf1-0/+14
For now, only monolithic shaders will hit the code path that will generate these intrinsics. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28408>
2024-03-28radeonsi/vcn: mark rc_per_pic as obsoletedBoyuan Zhang3-20/+22
Rename parameters in rc_per_pic to emphasize that the method is obsoleted Add warning to recommend users to update VCN FW for the correct rate control Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Ruijing Dong <ruijing.dong@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28234>
2024-03-28radeonsi/vcn: choose rc_per_pic by encode verisonBoyuan Zhang4-7/+59
Using VCN FW encode version to check if the current FW support the new rate control per picture method (ex). If not, roll back to use the previous rate control per picture method. Fixes: 5ecf83e9adcd652e6159 ("radeonsi/vcn: Implement separate QP for I/P/B frames") Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10793 Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Ruijing Dong <ruijing.dong@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28234>
2024-03-25radeonsi/vcn: update to use correct padding size.Ruijing Dong4-30/+33
Update padding size calculation to use cropping. Original method could result in 0 padding, which generated unnessary noise in the encoding result. Cc: mesa-stable Fixes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9196 Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Ruijing Dong <ruijing.dong@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28280>
2024-03-25radeonsi/vcn: add enc surface alignment capsRuijing Dong4-0/+37
set [64x16] as the alignment for hevc encoding surface. Cc: mesa-stable Reviewed-By: Sil Vilerino <sivileri@microsoft.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Ruijing Dong <ruijing.dong@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28280>
2024-03-25radeonsi/vpe: support vpe 1.1Alan Liu13-0/+504
update radeonsi and vpelib to support vpe 1.1 Co-authored-by: Alan Liu <haoping.liu@amd.com> Signed-off-by: Peyton Lee <peytolee@amd.com> Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28239>
2024-03-22radeonsi: implement the shader debug log from ac_nir_store_debug_log_amdMarek Olšák5-0/+73
This can be used to print values directly from shaders using ac_nir_store_debug_log_amd. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27952>
2024-03-22radeonsi: preserve alpha if needed in kill_ps_outputs_cbPierre-Eric Pelloux-Prayer1-0/+5
Some features (eg: ALPHA_TEST) relies on the alpha value being exported even if color_mask.a = false. In these cases, override comp_mask to preserve the alpha value. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10841 Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10845 Fixes: 6d2a7f53 ("radeonsi: decrease NUM_INTERP if export formats/colormask eliminated PS inputs") Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28268>
2024-03-21ac/llvm,radeonsi: fix memory leaks triggered by ac_nir_translate() errorsPatrick Lerda4-7/+6
For instance, this issue is triggered with "piglit/bin/glslparsertest tests/spec/arb_bindless_texture/compiler/images/arith-bound-image.frag pass 3.30 GL_ARB_bindless_texture GL_ARB_shader_image_load_store": Direct leak of 176 byte(s) in 1 object(s) allocated from: #0 0x7f84c3fbe9a7 in calloc (/usr/lib64/libasan.so.6+0xb19a7) #1 0x7f84ba7e0801 in ac_nir_translate ../src/amd/llvm/ac_nir_to_llvm.c:4391 #2 0x7f84ba53fdf4 in si_llvm_translate_nir ../src/gallium/drivers/radeonsi/si_shader_llvm.c:759 #3 0x7f84ba542bb7 in si_llvm_compile_shader ../src/gallium/drivers/radeonsi/si_shader_llvm.c:836 #4 0x7f84ba337b8e in si_compile_shader ../src/gallium/drivers/radeonsi/si_shader.c:2874 #5 0x7f84ba43a7c1 in si_init_shader_selector_async ../src/gallium/drivers/radeonsi/si_state_shaders.cpp:3176 #6 0x7f84b81c3448 in util_queue_thread_func ../src/util/u_queue.c:309 #7 0x7f84b821ea6a in impl_thrd_routine ../src/c11/impl/threads_posix.c:67 #8 0x7f84c2fea38a (/lib64/libc.so.6+0x8438a) Direct leak of 136 byte(s) in 1 object(s) allocated from: #0 0x7f84c3fbff57 in operator new(unsigned long) (/usr/lib64/libasan.so.6+0xb2f57) #1 0x7f84b1a5f749 in LLVMCreateBuilderInContext (/usr/local/lib64/libLLVM-17.so+0xc84749) #2 0x7f84ba7817b0 in ac_llvm_context_init ../src/amd/llvm/ac_llvm_build.c:54 #3 0x7f84ba542b7a in si_llvm_context_init ../src/gallium/drivers/radeonsi/si_shader_llvm.c:120 #4 0x7f84ba542b7a in si_llvm_compile_shader ../src/gallium/drivers/radeonsi/si_shader_llvm.c:832 #5 0x7f84ba337b8e in si_compile_shader ../src/gallium/drivers/radeonsi/si_shader.c:2874 #6 0x7f84ba43a7c1 in si_init_shader_selector_async ../src/gallium/drivers/radeonsi/si_state_shaders.cpp:3176 #7 0x7f84b81c3448 in util_queue_thread_func ../src/util/u_queue.c:309 #8 0x7f84b821ea6a in impl_thrd_routine ../src/c11/impl/threads_posix.c:67 #9 0x7f84c2fea38a (/lib64/libc.so.6+0x8438a) Indirect leak of 176 byte(s) in 1 object(s) allocated from: #0 0x7f84c3fbe7ef in __interceptor_malloc (/usr/lib64/libasan.so.6+0xb17ef) #1 0x7f84b81b9b3f in ralloc_size ../src/util/ralloc.c:118 #2 0x7f84b81b9fee in rzalloc_size ../src/util/ralloc.c:152 #3 0x7f84b81b9fee in rzalloc_array_size ../src/util/ralloc.c:232 #4 0x7f84b81b05c7 in _mesa_hash_table_init ../src/util/hash_table.c:163 #5 0x7f84b81b05c7 in _mesa_hash_table_create ../src/util/hash_table.c:186 #6 0x7f84ba7e06ae in ac_nir_translate ../src/amd/llvm/ac_nir_to_llvm.c:4381 #7 0x7f84ba53fdf4 in si_llvm_translate_nir ../src/gallium/drivers/radeonsi/si_shader_llvm.c:759 #8 0x7f84ba542bb7 in si_llvm_compile_shader ../src/gallium/drivers/radeonsi/si_shader_llvm.c:836 #9 0x7f84ba337b8e in si_compile_shader ../src/gallium/drivers/radeonsi/si_shader.c:2874 #10 0x7f84ba43a7c1 in si_init_shader_selector_async ../src/gallium/drivers/radeonsi/si_state_shaders.cpp:3176 #11 0x7f84b81c3448 in util_queue_thread_func ../src/util/u_queue.c:309 #12 0x7f84b821ea6a in impl_thrd_routine ../src/c11/impl/threads_posix.c:67 #13 0x7f84c2fea38a (/lib64/libc.so.6+0x8438a) Indirect leak of 176 byte(s) in 1 object(s) allocated from: #0 0x7f84c3fbe7ef in __interceptor_malloc (/usr/lib64/libasan.so.6+0xb17ef) #1 0x7f84b81b9b3f in ralloc_size ../src/util/ralloc.c:118 #2 0x7f84b81b9fee in rzalloc_size ../src/util/ralloc.c:152 #3 0x7f84b81b9fee in rzalloc_array_size ../src/util/ralloc.c:232 #4 0x7f84b81b05c7 in _mesa_hash_table_init ../src/util/hash_table.c:163 #5 0x7f84b81b05c7 in _mesa_hash_table_create ../src/util/hash_table.c:186 #6 0x7f84ba7e06e4 in ac_nir_translate ../src/amd/llvm/ac_nir_to_llvm.c:4382 #7 0x7f84ba53fdf4 in si_llvm_translate_nir ../src/gallium/drivers/radeonsi/si_shader_llvm.c:759 #8 0x7f84ba542bb7 in si_llvm_compile_shader ../src/gallium/drivers/radeonsi/si_shader_llvm.c:836 #9 0x7f84ba337b8e in si_compile_shader ../src/gallium/drivers/radeonsi/si_shader.c:2874 #10 0x7f84ba43a7c1 in si_init_shader_selector_async ../src/gallium/drivers/radeonsi/si_state_shaders.cpp:3176 #11 0x7f84b81c3448 in util_queue_thread_func ../src/util/u_queue.c:309 #12 0x7f84b821ea6a in impl_thrd_routine ../src/c11/impl/threads_posix.c:67 #13 0x7f84c2fea38a (/lib64/libc.so.6+0x8438a) Indirect leak of 128 byte(s) in 1 object(s) allocated from: #0 0x7f84c3fbe7ef in __interceptor_malloc (/usr/lib64/libasan.so.6+0xb17ef) #1 0x7f84b81b9b3f in ralloc_size ../src/util/ralloc.c:118 #2 0x7f84b81b046c in _mesa_hash_table_create ../src/util/hash_table.c:182 #3 0x7f84ba7e06e4 in ac_nir_translate ../src/amd/llvm/ac_nir_to_llvm.c:4382 #4 0x7f84ba53fdf4 in si_llvm_translate_nir ../src/gallium/drivers/radeonsi/si_shader_llvm.c:759 #5 0x7f84ba542bb7 in si_llvm_compile_shader ../src/gallium/drivers/radeonsi/si_shader_llvm.c:836 #6 0x7f84ba337b8e in si_compile_shader ../src/gallium/drivers/radeonsi/si_shader.c:2874 #7 0x7f84ba43a7c1 in si_init_shader_selector_async ../src/gallium/drivers/radeonsi/si_state_shaders.cpp:3176 #8 0x7f84b81c3448 in util_queue_thread_func ../src/util/u_queue.c:309 #9 0x7f84b821ea6a in impl_thrd_routine ../src/c11/impl/threads_posix.c:67 #10 0x7f84c2fea38a (/lib64/libc.so.6+0x8438a) Indirect leak of 128 byte(s) in 1 object(s) allocated from: #0 0x7f84c3fbe7ef in __interceptor_malloc (/usr/lib64/libasan.so.6+0xb17ef) #1 0x7f84b81b9b3f in ralloc_size ../src/util/ralloc.c:118 #2 0x7f84b81b046c in _mesa_hash_table_create ../src/util/hash_table.c:182 #3 0x7f84ba7e06ae in ac_nir_translate ../src/amd/llvm/ac_nir_to_llvm.c:4381 #4 0x7f84ba53fdf4 in si_llvm_translate_nir ../src/gallium/drivers/radeonsi/si_shader_llvm.c:759 #5 0x7f84ba542bb7 in si_llvm_compile_shader ../src/gallium/drivers/radeonsi/si_shader_llvm.c:836 #6 0x7f84ba337b8e in si_compile_shader ../src/gallium/drivers/radeonsi/si_shader.c:2874 #7 0x7f84ba43a7c1 in si_init_shader_selector_async ../src/gallium/drivers/radeonsi/si_state_shaders.cpp:3176 #8 0x7f84b81c3448 in util_queue_thread_func ../src/util/u_queue.c:309 #9 0x7f84b821ea6a in impl_thrd_routine ../src/c11/impl/threads_posix.c:67 #10 0x7f84c2fea38a (/lib64/libc.so.6+0x8438a) SUMMARY: AddressSanitizer: 920 byte(s) leaked in 6 allocation(s). Fixes: d92d35c9db6d ("ac/llvm: add a return value to ac_nir_translate") Signed-off-by: Patrick Lerda <patrick9876@free.fr> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28099>
2024-03-18radeonsi/ci: update failuresMarek Olšák3-2/+1
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28219>
2024-03-18radeonsi/ci: run GLCTS, ESCTS, and dEQP from the glcts directoryMarek Olšák1-15/+9
GLCTS contains more recent dEQP, so we can remove the deqp clone. Changes: - glcts should use the main branch - glcts/build contains gl-cts and deqp - glcts/build_es contains gles-cts - remove the escts and deqp directories and paths - it saves about 27 GB of disk space Updated build instructions: https://github.com/marekolsak/marek-build/ Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28219>
2024-03-18radeonsi/ci: udpate expected failuresEric Engestrom1-3/+100
https://gitlab.freedesktop.org/mesa/mesa/-/jobs/56378175 https://gitlab.freedesktop.org/mesa/mesa/-/jobs/56393368 https://gitlab.freedesktop.org/mesa/mesa/-/jobs/56414989 Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28246>
2024-03-15radeonsi: add test failures due to incorrect tests for nir_opt_varyingsMarek Olšák2-1/+213
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26819>
2024-03-15radeonsi: enable uniform propagation for varyings except VP/EnergyMarek Olšák3-0/+139
It regresses performance of VP/Energy. Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26819>
2024-03-15radeonsi: set trivial NIR options for nir_opt_varyingsMarek Olšák2-1/+3
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26819>
2024-03-15radeonsi: set the lower_mediump_io callback for GLSLMarek Olšák3-11/+15
It will be called by the GLSL linker before nir_opt_varyings. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26819>
2024-03-15radv: add a GPU hang workaround for legacy tess+GS for GFX10.3Samuel Pitoiset3-12/+19
Ported from RadeonSI ea94cb95e4dc6da8ee458db276942be1f72afa44 ("radeonsi/gfx10.3: add a GPU hang workaround for legacy tess+GS") Fixes: a23802bcb9a ("ac,radeonsi: start adding support for gfx10.3") Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28165>
2024-03-15radv: program SAMPLE_MASK_TRACKER_WATERMARK optimally for GFX11 APUsSamuel Pitoiset1-1/+4
Ported from RadeonSI 6ce3a958523dd0be97d9fb9e29af9336440b1213 ("radeonsi/gfx11: program SAMPLE_MASK_TRACKER_WATERMARK optimally for APUs") Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28165>
2024-03-15radv: fix programming of PA_SC_BINNER_CNTL_1.MAX_ALLOC_COUNT on GFX11Samuel Pitoiset1-2/+7
Ported from RadeonSI 7d3a414662ed4aaffd80762532a1c3c9f4cfc4f1 ("radeonsi/gfx11: fix programming of PA_SC_BINNER_CNTL_1.MAX_ALLOC_COUNT") Fixes: 25a66477d02 ("radeonsi/gfx11: register changes") Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28165>
2024-03-15radv: disable binning correctly on GFX11.5Samuel Pitoiset1-2/+4
Ported from RadeonSI 20445f296bfcf3be40436617aad5d8378ad09bce ("radeonsi: disable binning correctly on gfx11.5"). Fixes: b44a886b84c ("amd/common: add registers for gfx11.5") Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28165>
2024-03-15radeonsi: Only enable SEs that the device reportsFriedrich Vock1-8/+6
Matches PAL behavior. Cc: mesa-stable Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28196>
2024-03-14iris: Remove suballocation in iris_flush_resource()Kenneth Graunke1-52/+23
pipe->flush_resource() is called from eglCreateImageKHR in order to prepare images to be shared. It also has a valid context. We can just remove suballocation there, rather than doing it on the first dri_image_query like radeonsi does. This is much simpler and seems to work fine. Suggested-by: Michel Dänzer <mdaenzer@redhat.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13154>
2024-03-12radeonsi: don't test so many wave limits for AMD_TEST=testdmaperfMarek Olšák1-1/+2
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28119>
2024-03-12radeonsi: fix the DMA compute shaderMarek Olšák1-4/+6
It was correct for the parameters that the driver was using, but incorrect for other parameters. 1. The address computation must multiply the workgroup size (wave size) by num_mem_ops to fix the case when num_dwords_per_thread > 4. 2. nir_load_ssbo shouldn't set the number of components to 4 when num_dwords_per_thread < 4. Fixes: 6584088cd5e - radeonsi: "create_dma_compute" shader in nir Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28119>
2024-03-12radeonsi: derive htAlyssa Rosenzweig1-12/+2
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28056>
2024-03-11radeonsi: split RADEON_USAGE_NEEDS_IMPLICIT_SYNC into CB and DB flagsQiang Yu5-18/+23
it will be required in the future Signed-off-by: Qiang Yu <yuq825@gmail.com> Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27943>
2024-03-11radeonsi: add radeonsi_cache_rb_gl2 option enabling GL2 caching for CB and DBMarek Olšák2-22/+39
for perf testing Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27943>
2024-03-11radeonsi/gfx11: add missing DCC_RD_POLICY settingMarek Olšák1-1/+2
Fixes: 5acff16ce4e ("radeonsi: add a separate gfx10_init_gfx_preamble_state function") Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27943>
2024-03-11radeonsi/gfx11: program SAMPLE_MASK_TRACKER_WATERMARK optimally for APUsMarek Olšák1-2/+3
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27943>
2024-03-11radeonsi: program tessellation rings right before drawsMarek Olšák1-72/+42
so that we only wait for idle right before draw packets and all preceding SET packets can be processed in parallel with draws from the previous IB. This way we also don't need to update the preamble and flush the context just to emit the preamble. It's a normal state now. Use the new state atom that is emitted last. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27943>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-23 09:32:20 +0000