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2019-11-06Bump VERSION to 19.3.0-rc2mesa-19.3.0-rc2Dylan Baker1-1/+1
2019-11-05meson: Add dep_glvnd to egl deps when building with glvndDylan Baker1-1/+2
2019-11-05intel/compiler: remove the operand restriction for src1 on GLKPaulo Zanoni1-2/+1
2019-11-05aco: fix accidential reordering of instructions when schedulingDaniel Schürmann1-10/+47
2019-11-05aco: only use single-dword loads/stores for spillingDaniel Schürmann1-41/+10
2019-11-05aco: fix immediate offset for spills if scratch is usedDaniel Schürmann1-6/+6
2019-11-05anv: Properly handle host query reset of performance queriesLionel Landwerlin1-32/+20
2019-11-05iris: Fix "Force Zero RTA Index Enable" setting againKenneth Graunke1-1/+1
2019-11-05nir: correct use of identity check in pythonDylan Baker1-2/+2
2019-11-05radv: fix compute pipeline keys when optimizations are disabledSamuel Pitoiset1-2/+18
2019-11-05mesa: check draw buffer completeness on glClearBufferfi/glClearBufferivLionel Landwerlin1-0/+12
2019-11-05radv: Close all unnecessary fds in secure compile.Bas Nieuwenhuizen1-29/+64
2019-11-01docs/relnotes/new_features.txt: Add note about ACODaniel Schürmann1-0/+2
2019-10-31gallium/swr: Fix depth values for blit scenarioJan Zielinski1-0/+8
2019-10-31zink: emit line-width when using polygon line-modeErik Faye-Lund1-1/+20
2019-10-31pipe-loader: Build kmsro loader for with all kmsro targetsAlyssa Rosenzweig1-1/+10
2019-10-31anv: Set the batch allocator for compute pipelinesJason Ekstrand1-2/+5
2019-10-31anv/tests: Zero-initialize instancesJason Ekstrand6-6/+14
2019-10-31anv: Fix a potential BO handle leakJason Ekstrand1-1/+3
2019-10-31mesa: enable msaa in clear_with_quad if neededPierre-Eric Pelloux-Prayer1-0/+1
2019-10-31radv: Fix disk_cache_get size argument.Bas Nieuwenhuizen1-2/+2
2019-10-31anv: Remove _mesa_locale_init/fini calls.Bas Nieuwenhuizen1-3/+0
2019-10-31turnip: Remove _mesa_locale_init/fini calls.Bas Nieuwenhuizen1-3/+0
2019-10-31radv: Remove _mesa_locale_init/fini calls.Bas Nieuwenhuizen1-3/+0
2019-10-31radeonsi: tell the shader disk cache what IR is usedPierre-Eric Pelloux-Prayer1-7/+10
2019-10-31android: aco: fix Lower to CSSAMauro Rossi1-0/+1
2019-10-31iris/gen11+: Move flush for render target changeJordan Justen1-19/+20
2019-10-31iris: Add IRIS_DIRTY_RENDER_BUFFER state flagJordan Justen1-1/+3
2019-10-31intel/compiler: Report the number of non-spill/fill SEND messages on vec4 tooIan Romanick1-5/+35
2019-10-31radv: Fix timeout handling in syncobj wait.Bas Nieuwenhuizen1-1/+1
2019-10-31nv50/ir: mark STORE destination inputs as usedIlia Mirkin1-0/+6
2019-10-31intel/dev: set default num_eu_per_subslice on gen12Lionel Landwerlin1-1/+2
2019-10-31gm107/ir: fix loading z offset for layered 3d image bindingsIlia Mirkin4-54/+202
2019-10-30VERSION: bump to rc1mesa-19.3.0-rc1Dylan Baker1-1/+1
2019-10-30docs/relnotes/new_features.txt: Add note about gen12 support19.3-branchpointJordan Justen1-0/+1
2019-10-30intel/eu/validate/gen12: Add TGL to eu_validate tests.Jordan Justen1-0/+9
2019-10-30intel/dev: Add preliminary device info for TigerlakeJordan Justen2-0/+56
2019-10-30intel/dump_gpu: handle context create extended ioctlLionel Landwerlin1-0/+15
2019-10-30radv: Allocate space for temp. semaphore parts.Bas Nieuwenhuizen1-0/+1
2019-10-30anv: Add Tile Cache Flush for Unified Cache.Rafael Antognolli3-1/+45
2019-10-30blorp: Add Tile Cache Flush for Unified Cache.Rafael Antognolli1-0/+3
2019-10-30iris: Add Tile Cache Flush for Unified Cache.Rafael Antognolli2-0/+21
2019-10-30intel/genxml: Add gen12 tile cache flush bitJordan Justen1-0/+1
2019-10-30aco: implement VGPR spillingDaniel Schürmann1-7/+162
2019-10-30aco: always set scratch_offset in startpgmDaniel Schürmann3-23/+22
2019-10-30aco: omit linear VGPRs as spill variablesDaniel Schürmann1-4/+8
2019-10-30aco: ensure that spilled VGPR reloads are done after p_logical_startDaniel Schürmann1-34/+43
2019-10-30aco: simplify calculation of target register pressure when spillingDaniel Schürmann1-39/+12
2019-10-30aco: fix new_demand calculation for first instructionsRhys Perry1-4/+7
2019-10-30aco: don't add interferences between spilled phi operandsDaniel Schürmann1-8/+8