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2017-10-30Update version to 17.3.0-rc2mesa-17.3.0-rc2Emil Velikov1-1/+1
2017-10-27wayland-egl: fix wayland cflagsEric Engestrom1-1/+1
Fixes: 80bfff5c4f1d4d8c842a0 "wayland-egl: adds CFLAGS for wayland.egl.h include" Suggested-by: Daniel Stone <daniel@fooishbar.org> Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com> Acked-by: Emil Velikov <emil.velikov@collabora.com> Acked-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de> (cherry picked from commit 866c8a94d45fd88ea1e3a49c00a0ee5e589e4577)
2017-10-27vc4: fix release buildEric Engestrom1-6/+6
Mesa's DEBUG and assert's NDEBUG are not tied to each other, so we need to explicitly compile this code out. Fixes: 3df78928786134874eafa "vc4: Drop reloc_count tracking for debug asserts on non-debug builds." Cc: Eric Anholt <eric@anholt.net> Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com> Reviewed-by: Eric Anholt <eric@anholt.net> (cherry picked from commit 5d44e35a8f3967b40db153fdcedb9294d44ae5c4)
2017-10-27radeonsi: update hack for HTILE corruption in ARK: Survival EvolvedSamuel Pitoiset6-13/+13
It appears that flushing the DB metadata is actually not sufficient since the driver uses the new VS blit shaders. This looks quite strange though, but it seems like we need to flush DB for fixing the corruption. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102955 Fixes: 69ccb9dae7 (radeonsi: use new VS blit shaders (VS inputs in SGPRs) Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit dd79aa4ad30df205076be25f6bbf42768abea20a)
2017-10-27meson: wayland-egl depends on wayland-clientDaniel Stone1-0/+1
Since wayland-egl.h is currently provided by the core Wayland package, depend on wayland-client to make sure we get it in our include path. Signed-off-by: Daniel Stone <daniels@collabora.com> Acked-by: Emil Velikov <emil.velikov@collabora.com> Fixes: 108d257a16 ("meson: build libEGL") Cc: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de> Cc: Dylan Baker <dylan@pnwbakers.com> Cc: Gert Wollny <gw.fossdev@gmail.com> (cherry picked from commit 9f7ed60b3eae9d3d20805e79c9ab67674619e2cd)
2017-10-27intel/eu: Use EXECUTE_1 for JMPIJason Ekstrand2-2/+1
The PRM says "The execution size must be 1." In 73137997e23ff6c11, the execution size was set to 1 when it should have been BRW_EXECUTE_1 (which maps to 0). Later, in dc2d3a7f5c217a7cee9, JMPI was used for line AA on gen6 and earlier and we started manually stomping the exeution size to BRW_EXECUTE_1 in the generator. This commit fixes the original bug and makes brw_JMPI just do the right thing. Reviewed-by: Matt Turner <mattst88@gmail.com> Fixes: 73137997e23ff6c1145d036315d1a9ad96651281 (cherry picked from commit 562b8d458c2de262019da2c056f75cb9feb5ee54)
2017-10-27radv: Fix truncation issue hexifying the cache uuid for the disk cache.Bas Nieuwenhuizen1-2/+2
Going from binary to hex has a 2x blowup. Fixes: 14216252923 'radv: create on-disk shader cache' Reviewed-by: Dave Airlie <airlied@redhat.com> (cherry picked from commit 5bfbab2fdcc5b1fcb3a0d0b8cce19c5492c7de68)
2017-10-27i965: Fix memmem compiler warnings.Eric Anholt1-1/+2
gcc is throwing this warning in my meson build: ../src/intel/compiler/brw_eu_validate.c:50:11: warning argument 1 null where non-null expected [-Wnonnull] return memmem(haystack.str, haystack.len, ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ needle.str, needle.len) != NULL; ~~~~~~~~~~~~~~~~~~~~~~~ The first check for CONTAINS has a NULL error_msg.str and 0 len. The glibc implementation will exit without looking at any haystack bytes if haystack.len < needle.len, so this was safe, but silence the warning anyway by guarding against implementation variablility. Fixes: 122ef3799d56 ("i965: Only insert error message if not already present") Reviewed-by: Matt Turner <mattst88@gmail.com> (cherry picked from commit e91c3540fc620b39a16d5bce9fd75aa0ddd7ed7e)
2017-10-27radv: move nir print after linking is doneTimothy Arceri2-3/+8
We now have linking optimisations so we want to delay dumping the nir until after these are complete. Fixes: 06f05040eb73 (radv: Link shaders) Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit f0a2bbd1a4a0caf85d91469e61d01a126cfc2a36) Squashed with commit: radv: print NIR before LLVM IR and disassembly It's still printed after linking, but it makes more sense to have SPIRV->NIR->LLVM IR->ASM. Fixes: f0a2bbd1a4 (radv: move nir print after linking is done) Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit 9711979df007859de86fc08c20c826a71d10a660)
2017-10-27mesa/bufferobj: don't double negate the rangeDave Airlie1-3/+3
This fixes a regression I introduced refactoring this code, I managed to invert range twice, I moved the inversion into the common code, but forgot to stop doing it in the callee. Fixes: GL45-CTS.multi_bind.dispatch_bind_buffers_base Fixes: 35ac13ed3 (mesa/bufferobj: consolidate some codepaths between ubo/ssbo/atomics.) Reported-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com> (cherry picked from commit 11d688d9f0d2ee4d0178d1807c0075e5e8364b1d)
2017-10-27radv: clone meta shaders before linkingTimothy Arceri1-1/+8
The IR is reused in different pipeline combinations so we need to clone it to avoid link time optimistaions messing up the original copy. Fixes: 06f05040eb73 (radv: Link shaders) Reviewed-by: Dave Airlie <airlied@redhat.com> (cherry picked from commit 013313cf895e4d47b2631d5f4dd32fcbce2b0a17)
2017-10-27meson: fix egl build for meson version < 0.43Dylan Baker1-5/+4
Meson 0.43 added the ability to pass nested lists to include_directories, so the code that we have works for 0.43, but not for 0.42. This patch changes the include_directories list to be flat so it works with 0.42 fixes: 108d257a16859898f5c ("meson: build libEGL") Tested-by: Vinson Lee <vlee@freedesktop.org> Reviewed-by: Rhys Kidd <rhyskidd@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com> (cherry picked from commit 77f7ef0287cee23d411b1a2e750d281efe425ff3)
2017-10-27mesa: Accept GL_BACK in get_fb0_attachment with ARB_ES3_1_compatibility.Kenneth Graunke1-0/+9
According to the ARB_ES3_1_compatibility specification, glGetFramebufferAttachmentParameteriv is supposed to accept BACK, and it behaves exactly like BACK_LEFT. Fixes a GL error in GFXBench 5 Aztec Ruins. Cc: "17.3 17.2" <mesa-stable@lists.freedesktop.org> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> (cherry picked from commit 4f538c3f99b25dc96cd20314ce7785fd4d333be1)
2017-10-27i965: unref push_const_bo in intelDestroyContextTapani Pälli1-0/+6
Valgrind shows that leak is caused by gen6_upload_push_constant, add unref push_const_bo per stage to destructor to fix this (like done for scratch_bo). ==10952== 144 bytes in 1 blocks are definitely lost in loss record 44 of 66 ==10952== at 0x4C30A1E: calloc (vg_replace_malloc.c:711) ==10952== by 0x8C02847: bo_alloc_internal.constprop.10 (brw_bufmgr.c:344) ==10952== by 0x8C425C4: intel_upload_space (intel_upload.c:101) ==10952== by 0x8C22ED0: gen6_upload_push_constants (gen6_constant_state.c:154) v2: remove if conditions, brw_bo_unreference handles NULL (Ken, Emil) Fixes: 24891d7c05 ("i965: Store per-stage push constant BO pointers.") Signed-off-by: Tapani Pälli <tapani.palli@intel.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 0b131ca427d788ae08426bdeddb8f4bd3c7da202)
2017-10-27i965/miptree: Take an isl_format in render_aux_usageJason Ekstrand5-27/+39
Not all rendering matches the miptree format. We allow rendering to texture views so there are cases where it may not match. In those cases, our current scheme of just passing the value of ctx->sRGBEnabled isn't viable. Instead, just do what we do for texturing and pass the view format in directly. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 39c5c12f8fbee9eec26a627f247d1f3ef7d4bf39)
2017-10-27i965/blorp: Use more temporary isl_format variablesJason Ekstrand1-8/+7
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 78e50185d6f9546f8b09cf281f5e5a17195a7ee5)
2017-10-27i965/blorp: Use blorp_to_isl_format for src_isl_format in blit_miptreesJason Ekstrand1-1/+2
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 94389943b63bf8e25fecbbdf357ae5da100d2fc9)
2017-10-27spirv: Claim support for the simple memory modelJason Ekstrand1-1/+2
It's rather surprising that we've never actually hit this before. Aparently, Ian's SPIR-V generator currently claims the Simple when you don't do anything complex. We really shouldn't assert-fail on it. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 8ab9820d34d3a454e455c99e28ed2b6031b25b0f)
2017-10-27radeonsi: add a workaround for weird s_buffer_load_dword behavior on SIMarek Olšák1-3/+10
See my LLVM patch which fixes the root cause. Users have to apply this patch and then they have 2 choices: - Downgrade to LLVM 5.0 - Update to LLVM git after my LLVM patch is pushed. It won't be possible to use current and earlier development version of LLVM 6.0. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Cc: 17.3 <mesa-stable@lists.freedesktop.org> (cherry picked from commit 3f8e3c2bd8f54ae6817f7496be47f4e1a8860d9c)
2017-10-27radeon/video: add gfx9 offsets when rejoin the video surfaceLeo Liu1-1/+4
For CPU access. Signed-off-by: Leo Liu <leo.liu@amd.com> Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Christian König <christian.koenig@amd.com> (cherry picked from commit ea3dc75d72c148dabffa71e8657bfd831ad0afe9)
2017-10-27anv/pipeline: Call nir_lower_system_valaues after brw_preprocess_nirJason Ekstrand1-1/+2
We currently have a bug where nir_lower_system_values gets called before nir_lower_var_copies so it will miss any system value uses which come from a copy_var intrinsic. Moving it to after brw_preprocess_nir fixes this problem. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 279f8fb69cf68d05287e14f60cf67fc025643bc4)
2017-10-27anv/pipeline: Drop nir_lower_clip_cull_distance_arraysJason Ekstrand1-2/+0
We already handle it in brw_preprocess_nir Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (cherry picked from commit afa0ddb81e693678069c630751e2091eea796937)
2017-10-27intel/fs: Handle flag read/write aliasing in needs_src_copyJason Ekstrand1-1/+3
In order to implement the ballot intrinsic, we do a MOV from flag register to some GRF. If that GRF is used in a SEL, cmod propagation helpfully changes it into a MOV from the flag register with a cmod. This is perfectly valid but when lower_simd_width comes along, it simply splits into two instructions which both have conditional modifiers. This is a problem since we're reading the flag register. This commit makes us check whether or not flags_written() overlaps with the flag values that we are reading via the instruction source and, if we have any interference, will force us to emit a copy of the source. Reviewed-by: Matt Turner <mattst88@gmail.com> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit fa6e74e33e5bc5f6fba8f9de76b8b059515e708f)
2017-10-27clover: Fix compilation after clang r315871Jan Vesely2-5/+12
v2: use a more generic compat function v3: rename and formatting cleanup Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103388 Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Francisco Jerez <currojerez@riseup.net> CC: <mesa-stable@lists.freedesktop.org> (cherry picked from commit a6d38f476beaaf0a9677cfc168172121b5779570)
2017-10-27nir/intrinsics: Set the correct num_indices for load_outputJason Ekstrand1-1/+1
Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> (cherry picked from commit c1b84256ccc443a9792893bc780bba970c0dcd4e)
2017-10-27ac/nir: generate correct instruction for atomic min/max on unsigned imagesMatthew Nicholls1-2/+4
v2: fix silly typo Cc: "17.2 17.3" <mesa-stable@lists.freedesktop.org> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (cherry picked from commit 27a0b24bf238342031e0709584e4d71ab228f1ec)
2017-10-27radv: use device name in cache creation like radeonsi.Dave Airlie1-2/+3
Not sure how useful this is, but it makes it more consistent. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Cc: "17.3" <mesa-stable@lists.freedesktop.org> Signed-off-by: Dave Airlie <airlied@redhat.com> (cherry picked from commit d8cefaa197f02944812ef535b1b303dd5bf26848)
2017-10-27radv: Update code pointer correctly if a variant is already createdAlex Smith1-0/+2
This was the actual cause of GPU hangs fixed by 0fdd531457ec ("radv: Fix pipeline cache locking issues"), since multiple threads would end up trying to create the variants for a single entry. Now that we're locking around the whole of this function, this isn't really necessary (we either create all or none of the variants), but fix this anyway in case things change later. Signed-off-by: Alex Smith <asmith@feralinteractive.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> CC: 17.3 <mesa-stable@lists.freedesktop.org> (cherry picked from commit fee9d05e2136b2b7c5a1ad2be7180b99f733f539)
2017-10-27i965: Revert absolute mode for constant buffer pointers.Kenneth Graunke2-25/+1
The kernel doesn't initialize the value of the INSTPM or CS_DEBUG_MODE2 registers at context initialization time. Instead, they're inherited from whatever happened to be running on the GPU prior to first run of a new context. So, when we started setting these, other contexts in the system started inheriting our values. Since this controls whether 3DSTATE_CONSTANT_* takes a pointer or an offset, getting the wrong setting is fatal for almost any process which isn't expecting this. Unfortunately, VA-API and Beignet don't initialize this (nor does older Mesa), so they will die horribly if we start doing this. UXA and SNA don't use any push constants, so they are unaffected. Until we have some kind of solution to this problem, I'm going to revert this patch and abandon using the feature for now. It will lead to fewer pushed UBO ranges on Broadwell+, which may lead to lower performance, though I don't have any data on the impact. Cc: "17.3 17.2" <mesa-stable@lists.freedesktop.org> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102774 (cherry picked from commit 013d33122028f2492da90a03ae4bc1dab84c3ee9)
2017-10-27amd/common/gfx9: workaround DCC corruption more conservativelyNicolai Hähnle1-7/+25
Fixes KHR-GL45.texture_swizzle.smoke and others on Vega. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102809 Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Marek Olšák <marek.olsak@amd.com> (cherry picked from commit f9ccfda9bc8166f833fdb64adf1eca5b8ee69251)
2017-10-27glsl: fix derived cs variablesIlia Mirkin9-118/+244
There are two issues with the current implementation. First, it relies on the layout(local_size_*) happening in the same shader as the main function, and secondly it doesn't work for variable group sizes. In both cases, the simplest fix is to move the setup of these derived values to a later time, similar to how the gl_VertexID workarounds are done. There already exist system values defined for both of the derived values, so we use them unconditionally, and lower them after linking is performed. While we're at it, we move to using gl_LocalGroupSizeARB instead of gl_WorkGroupSize for variable group sizes. Also the dead code elimination avoidance can be removed, since there can be situations where gl_LocalGroupSizeARB is needed but has not been inserted for the shader with main function. As a result, the lowering code has to insert its own copies of the system values if needed. Reported-by: Stephane Chevigny <stephane.chevigny@polymtl.ca> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103393 Cc: mesa-stable@lists.freedesktop.org Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> (cherry picked from commit 4d24a7cb97641cacecd371d1968f6964785822e4)
2017-10-23Update version to 17.3.0-rc1mesa-17.3.0-rc1Emil Velikov1-1/+1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2017-10-23radv: automake: include radv_extensions.py in the tarball17.3-branchpointJuan A. Suarez Romero1-0/+1
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-10-23ac/nir: Only clamp shadow reference on radeonsi.Bas Nieuwenhuizen4-2/+9
Vulkan CTS does not expect the value to be clamped (at least for D32), and it makes a differences even though depth is in [0,1], due to strict inequalities. I couldn't find anything in the Vulkan spec about this, but the test seemed to be copied from GL tests and the GL spec only specifies clamping for fixed point formats. Hence I expect radeonsi to run into this at some point as well, but given that they still have a usecase with the Z16->Z32 promotion, I'll leave that for someone else to clean up. This at least fixes radv dEQP-VK.texture.shadow.* on VI. Fixes: 0f9e32519bb 'ac/nir: clamp shadow texture comparison value on VI' Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-23radv: Disallow indirect outputs for GS on GFX9 as well.Bas Nieuwenhuizen1-3/+1
Since it also uses the output vector before writing to memory. Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."' Reviewed-by: Dave Airlie <airlied@redhat.com> Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-10-23ac/nir: Fix nir_texop_lod on GFX for 1D arrays.Bas Nieuwenhuizen1-1/+3
Fixes: 1bcb953e166 'radv: handle GFX9 1D textures' Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-23radv/ac/nir: only emit tess factors to storage if tes reads themDave Airlie3-2/+4
Otherwise we just need to write them to the tf ring. this seems to improve the tessellation demo on Bonarie ~2190->~2230 fps Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-22radv: Don't use vgpr indexing for outputs on GFX9.Bas Nieuwenhuizen1-0/+5
Due to LLVM bugs. Fixes a bunch of dEQP-VK.glsl.indexing.* tests. Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."' Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-21ac/nir: Account for compact array index in GS input load from LDS.Bas Nieuwenhuizen1-1/+1
Mirrors the vram path. Fixes: d4ecc3c9299 'ac/nir: Add loading from LDS for merged GS.' Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-21radv: Don't compile shaders when they are cached already.Bas Nieuwenhuizen1-19/+23
When the gs_copy_shader is NULL (due to an incomplete cache), but the main shaders are found, we still do the nir, but we shouldn't compile the shaders again. For merged shaders we should also account for the missing shaders. Fixes: ce03c119ce0 'radv: Add code to compile merged shaders.' Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-21radv: Don't check for max GL GS invocations.Bas Nieuwenhuizen1-2/+0
We specify 127 instead of 32 as the limit in vulkan. Fixes: 6bc42855f92 'radv: enable GS on GFX9' Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-21radv: Don't explicitly reference vertex shader for draw_id.Bas Nieuwenhuizen1-1/+1
With merged shaders the vertex shader may not exist. This got in because the offending patch was written before merged shaders were upstream, but committed after. Fixes: 75dfab24a2c 'radv: refactor indirect draws with radv_draw_info' Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-10-21radv: Don't reset cmd_buffer->state.dirty.Bas Nieuwenhuizen1-2/+0
Otherwise for non-indexed draws we set and immediately unset RADV_CMD_DIRTY_INDEX_BUFFER. As all the set functions should clear their own bit, this is unnecessary. Fixes: 341529dbee5 'radv: use optimal packet order for draws' Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-10-21radv: Correctly detect changed shaders for vertex descriptors.Bas Nieuwenhuizen1-6/+6
As they were emitted after the new pipeline, the changed pipeline detection was not working anymore. Fixes: 341529dbee5 'radv: use optimal packet order for draws' Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-10-21ac/nir: Set larged wrokgroup size for GS on GFX9.Bas Nieuwenhuizen1-1/+1
They don't take a single wave anymore and we need the barriers. Fixes: 6bc42855f92 'radv: enable GS on GFX9' Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-21ac/nir: Take the max workgroup size of all provided shaders.Bas Nieuwenhuizen1-1/+6
Fixes: ffaf4d608a1 'radv: Enable tessellation shaders for GFX9.' Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-21radv: Fix pipeline cache locking issuesAlex Smith1-7/+23
Need to lock around the whole process of retrieving cached shaders, and around GetPipelineCacheData. This fixes GPU hangs observed when creating multiple pipelines in parallel, which appeared to be due to invalid shader code being pulled from the cache. Signed-off-by: Alex Smith <asmith@feralinteractive.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-21anv: don't assert on device init on CannonlakeLionel Landwerlin1-2/+4
v2: Warn that support is still in alpha (Jason) Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-10-21anv: disable stencil pma fix on Gen > 9Lionel Landwerlin1-0/+2
This workaround isn't listed on Gen10. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-10-21blorp: enable R32G32B32X32 blorp ccs copiesLionel Landwerlin1-0/+1
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
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