AgeCommit message (Expand)AuthorFilesLines
2017-10-23Update version to 17.3.0-rc1mesa-17.3.0-rc1Emil Velikov1-1/+1
2017-10-23radv: automake: include in the tarball17.3-branchpointJuan A. Suarez Romero1-0/+1
2017-10-23ac/nir: Only clamp shadow reference on radeonsi.Bas Nieuwenhuizen4-2/+9
2017-10-23radv: Disallow indirect outputs for GS on GFX9 as well.Bas Nieuwenhuizen1-3/+1
2017-10-23ac/nir: Fix nir_texop_lod on GFX for 1D arrays.Bas Nieuwenhuizen1-1/+3
2017-10-23radv/ac/nir: only emit tess factors to storage if tes reads themDave Airlie3-2/+4
2017-10-22radv: Don't use vgpr indexing for outputs on GFX9.Bas Nieuwenhuizen1-0/+5
2017-10-21ac/nir: Account for compact array index in GS input load from LDS.Bas Nieuwenhuizen1-1/+1
2017-10-21radv: Don't compile shaders when they are cached already.Bas Nieuwenhuizen1-19/+23
2017-10-21radv: Don't check for max GL GS invocations.Bas Nieuwenhuizen1-2/+0
2017-10-21radv: Don't explicitly reference vertex shader for draw_id.Bas Nieuwenhuizen1-1/+1
2017-10-21radv: Don't reset cmd_buffer->state.dirty.Bas Nieuwenhuizen1-2/+0
2017-10-21radv: Correctly detect changed shaders for vertex descriptors.Bas Nieuwenhuizen1-6/+6
2017-10-21ac/nir: Set larged wrokgroup size for GS on GFX9.Bas Nieuwenhuizen1-1/+1
2017-10-21ac/nir: Take the max workgroup size of all provided shaders.Bas Nieuwenhuizen1-1/+6
2017-10-21radv: Fix pipeline cache locking issuesAlex Smith1-7/+23
2017-10-21anv: don't assert on device init on CannonlakeLionel Landwerlin1-2/+4
2017-10-21anv: disable stencil pma fix on Gen > 9Lionel Landwerlin1-0/+2
2017-10-21blorp: enable R32G32B32X32 blorp ccs copiesLionel Landwerlin1-0/+1
2017-10-20meson: Fix vc5 deps on the XML-generated headers.Eric Anholt2-2/+2
2017-10-20broadcom/vc5: Propagate vc4 aliasing fix to vc5.Eric Anholt1-1/+1
2017-10-20broadcom/vc4: Fix aliasing issueStefan Schake1-1/+1
2017-10-20meson: Add support for EGL glvndDylan Baker1-2/+44
2017-10-20meson: build libEGLDylan Baker9-35/+304
2017-10-20meson: move wayland_drm_protocol generation to wayland-drmDylan Baker2-15/+13
2017-10-20meson: Don't allow glx to be built without platform_x11Dylan Baker1-2/+6
2017-10-20meson: bump libdrm_amdgpu requirement to 2.4.85Dylan Baker1-1/+1
2017-10-20nir: Print the components referenced for split or packed shader in/outs.Eric Anholt1-1/+25
2017-10-20nir: Add a safety check that we don't remove dead I/O vars after lowering.Eric Anholt1-4/+14
2017-10-21radv: disable implicit sync for radv allocated bos v3Andres Rodriguez4-1/+8
2017-10-21radv: factor out radv_alloc_memoryAndres Rodriguez2-5/+25
2017-10-21radv: Expose VK_EXT_global_priorityAndres Rodriguez4-0/+5
2017-10-21radv: don't skip PS/VS partial flushAndres Rodriguez1-8/+6
2017-10-21radv: Implement VK_EXT_global_priorityAndres Rodriguez4-8/+62
2017-10-21radeonsi: hardcode shader WAVE_LIMIT to the maximum valueAndres Rodriguez1-7/+14
2017-10-21radv: hardcode shader WAVE_LIMIT to the maximum valueAndres Rodriguez1-9/+18
2017-10-21vulkan: update headers & registry to VK 1.0.63Andres Rodriguez2-86/+213 Bump libdrm_amdgpu version to 2.4.85.Bas Nieuwenhuizen1-1/+1
2017-10-20broadcom/vc5: Use SETMSF to handle discards.Eric Anholt2-25/+12
2017-10-20broadcom/vc5: Set the snorm/unorm packing functions to be lowered.Eric Anholt1-0/+4
2017-10-20broadcom/vc5: Fix pasteo that broke vertex texturing.Eric Anholt1-1/+1
2017-10-20broadcom/vc5: Move default attribute value setup to the CSO and fix them.Eric Anholt3-29/+23
2017-10-20broadcom/vc5: Move most of the shader state attribute record to the CSO.Eric Anholt4-65/+90
2017-10-20broadcom/vc5: Fix build failure frm nir_shader::stage removal.Eric Anholt1-4/+4
2017-10-20i965/fs: Use align1 mode on ternary instructions on Gen10+Matt Turner1-4/+8
2017-10-20i965: Add align1 ternary instruction emission supportMatt Turner1-55/+160
2017-10-20i965: Add align1 ternary instruction disassembler supportMatt Turner2-75/+288
2017-10-20i965: Add align1 ternary instruction-word supportMatt Turner1-0/+108
2017-10-20i965: Add align1 ternary instruction support to conversion functionsMatt Turner4-34/+101
2017-10-20i965: Add align1 ternary instruction field encodingsMatt Turner1-0/+35