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2021-05-05mesa: NOTE! Default branch is now mainmasterJordan Justen0-0/+0
To update your local repository to use the new default branch, these commands may help: $ git fetch origin $ git checkout master $ git branch -m main $ git branch --set-upstream-to=origin/main $ git remote set-head origin --auto Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2021-05-05docs: Rename master branch to mainJordan Justen6-23/+23
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2021-05-05docs/releasing.rst: Rename master branch to mainJordan Justen1-5/+5
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2021-05-05issue_templates/Bug Report: Rename master branch to mainJordan Justen2-2/+2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2021-05-05.gitlab-ci.yml: Use main branch for gitlab ciJordan Justen1-4/+4
Reworks: * Fix mesa/mesamaster typo to mesa/mesa main (anholt) * Use $CI_DEFAULT_BRANCH (eric_engestrom) Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2021-05-05bin/pick: Rename master branch to mainJordan Justen3-10/+10
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com> Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2021-05-05commit_in_branch_test.py: Rename branch master to mainJordan Justen1-9/+9
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Dylan Baker <dylan@pnwbakers.com> Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2021-05-05docs: remove doxygen supportErik Faye-Lund29-5980/+0
It seems building the doxygen docs has bit-rotted over time, and now generates a set of empty modules, apart from some basic descriptions. Since Mesa is mostly implementing externally documented APIs, I don't think it makes a whole lot of sense trying to fix this, and I think the presence of these files might confuse users who try them out. So let's just get rid of this. Reviewed-by: Jose Fonseca <jfonseca@vmware.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10611>
2021-05-05ci/lavapipe: Add fractional NIR stress test job.Emma Anholt1-0/+13
I think between the disk cache unit tests and testing that we can really serialize/deserialize NIR, this covers what I cared about for testing disk caching. Closes: #3597 Reviewed-by: Adam Jackson <ajax@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10629>
2021-05-05ci/llvmpipe: Add testing of gles3/31/gl.Emma Anholt3-0/+88
llvmpipe is a pretty important driver, we should be fully testing it. Also, enable some options to stress test some NIR internals. Reviewed-by: Adam Jackson <ajax@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10629>
2021-05-05turnip: Demote API version to 1.1.Eric Anholt2-5/+1
We don't support major 1.2 required extensions like timeline semaphores. Fixes many complaints in the dEQP-VK.info.vulkan1p2.* group. We were originally bumped to 1.2 in 75755e0eba17 ("turnip: Pretend to support Vulkan 1.2") but hopefully that build issue has been fixed in the entrypoint reworks since then. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10471>
2021-05-05venus: populate VK_ERROR_OUT_OF_HOST_MEMORY if appliedYiwei Zhang1-9/+12
Fix dEQP-VK.wsi.android.swapchain.simulate_oom.* failures. Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org> Reviewed-by: Chia-I Wu <olvaffe@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10639>
2021-05-05freedreno/a5xx: Remove ppgtt hackErik Faye-Lund1-10/+0
This should no longer be needed after !7773, which fixes the issue that lead to the crash. Sorry for not fixing the issue earlier ;) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10645>
2021-05-05aux/cso_cache: add handling for save/restore of compute statesMike Blumenkrantz2-1/+105
just shader and samplers for now Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10616>
2021-05-05panfrost: Fix format definitions to match gallium expectationsBoris Brezillon3-43/+31
Gallium wants the depth or stencil component replicated on all .XYZW. That's easily done on pre-v7 since we can forge all the swizzles we want, but Bifrost v7 only supports a few combinations, so we have to combine the user swizzle with our own 'replicate' swizzle to make it work. Note that v7 has a trick to make border color work when the GRBA order is chosen: they apply the red border color to the green component. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10612>
2021-05-05android: pan/bi: add bi_opt_constant_fold.c to Makefile.sourcesMauro Rossi1-0/+1
Fixes the following building error: FAILED: out/target/product/x86_64/obj/SHARED_LIBRARIES/gallium_dri_intermediates/LINKED/gallium_dri.so ... ld.lld: error: undefined symbol: bi_opt_constant_fold >>> referenced by bifrost_compile.c:3105 (external/mesa/src/panfrost/bifrost/bifrost_compile.c:3105) Fixes: 1cb11969bec0 ("pan/bi: Add simple constant folding pass") Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10603>
2021-05-05anv: Allow storage on all formats that support typed writesJason Ekstrand3-12/+39
In particular, this gives us B8G8R8A8_UNORM storage support which is useful for writing WSI images from compute shaders. These formats can only be accessed in a spec-compliant way by decorating the variable NonReadable in the SPIR-V (writeonly in GLSL). If the client doesn't so decorate the variable, it'll get the null surface state where reads return 0 and writes are ignored. Tested-by: Simon Ser <contact@emersion.fr> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10624>
2021-05-05isl: document format fieldsLionel Landwerlin1-0/+2
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10624>
2021-05-05anv: Check offset instead of alloc_size for freeing surface statesJason Ekstrand1-4/+8
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10624>
2021-05-05gallium/u_vbuf: avoid dereferencing NULL pointerErik Faye-Lund3-5/+6
When I last time fixed this, I missed that continuing here would make us leak pointers in the translate state, which is what made this avoid a crash in the first place. That's not great, we need to set *some* pointer in this case. The obvious option would be NULL, but that means that the translate-code also needs to support NULL-pointers here. Instead, let's point to a small, static buffer that contains enough zero-data for the largest possible vertex attribute. This avoids having to add more NULL-checks. Fixes: a8e8204b186 ("gallium/u_vbuf: support NULL-resources") Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7773>
2021-05-05radeon/vcn: Use the correct pitch for chroma surface.Bas Nieuwenhuizen1-2/+2
The pitch of the chroma plane isn't necessarily half that of the luma plane, as tiling (and presumably even linear) swizzle modes apply some alignment. Fixes: 35e25ea1d07 ("ac/surface: allow non-DCC modifiers for YUV on GFX9+") Reviewed-by: James Zhu <James.Zhu@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10638>
2021-05-05turnip: implement VK_KHR_vulkan_memory_modelDanylo Piliaiev6-21/+112
No handling of Acquire/Release because at the moment scheduler works as if any barrier is Acq+Rel. Instead of removing scoped_barrier with scope/mode that for TCS corresponds to a control_barrier or a memory_barrier_tcs_patch in ir3_nir_lower_tess_ctrl - remove them in emit_intrinsic_barrier. And do the same for memory_barrier_tcs_patch and control_barrier. While in any case hw fence/barrier shouldn't be emitted for them, they still affect ordering of stores, and in feature ir3 backend may want to have that information. Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9054>
2021-05-05ir3: update bar/fence bits in accordance to blobDanylo Piliaiev1-4/+11
On a6xx blob uses .l rather differently from a5xx. Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9054>
2021-05-05ir3: memory_barrier also controls shared memory access orderDanylo Piliaiev3-15/+2
nir_intrinsic_memory_barrier has the same semantic as memoryBarrier() in GLSL, which is: GLSL 4.60, 4.10. "Memory Qualifiers": "The built-in function memoryBarrier() can be used if needed to guarantee the completion and relative ordering of memory accesses performed by a single shader invocation." GLSL 4.60, 8.17. "Shader Memory Control Functions": "The built-in functions memoryBarrier() and groupMemoryBarrier() wait for the completion of accesses to all of the above variable types." Fixes tests: dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_local.image.guard_nonlocal.workgroup.comp dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_nonlocal.workgroup.guard_local.image.comp Fixes: 819a613a ("freedreno/ir3: moar better scheduler") Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com> Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9054>
2021-05-05docs: do not generate redirects on errorErik Faye-Lund1-2/+2
The build-finished event is also triggered when there's an error. I somehow got the second argument wrong, and ended up ignoring the case. This can lead to new exceptions being thrown due to missing files, that ends up hiding the real problem. Fixes: 64a4ba9e1ce ("docs: add an extension to generate redirects") Reviewed-by: Eric Engestrom <eric@engestrom.ch> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10407>
2021-05-05zink: only emit ImageBuffer cap if neededErik Faye-Lund1-1/+2
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10371>
2021-05-05zink: emit cap earlyErik Faye-Lund1-2/+4
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10371>
2021-05-05zink: emit sample-shading cap earlyErik Faye-Lund1-8/+4
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10371>
2021-05-05zink: remove needless shader-info from contextErik Faye-Lund1-4/+0
There's no longer any code reading this, so let's get rid of it. It always rubbed me a bit the wrong way, because this repeated some information already present in the context. Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10371>
2021-05-05zink: emit cap earlyErik Faye-Lund1-2/+6
We have enough information to emit this cap early, so let's do that. Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10371>
2021-05-05zink: do not check for varying output for fragment shadersErik Faye-Lund1-2/+3
This will make us emit these caps needlessly, possibly on implementations not supporting the enabling features. Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10371>
2021-05-05zink: always enable fixed shader-capsErik Faye-Lund1-10/+5
This is required for a bunch of stuff that can occur in any Vulkan shader stage, not just these few. So let's always emit this cap. Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10371>
2021-05-05intel/decoder: add gen4/5 geometry state decodeDave Airlie1-0/+24
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10642>
2021-05-05intel/decoder: fixup batch decoder for binding tables on gen4/5Dave Airlie1-4/+13
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10642>
2021-05-05radv: expose 2/3rd of total memory as VRAM and 1/3rd as GTT on APUsSamuel Pitoiset1-32/+84
A bunch of games complain when the VRAM size is too small. The most compatible solution seems to return memory heaps like a dGPU. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3423 Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9774>
2021-05-05radv: adjust the computation of the total usage of memory usedSamuel Pitoiset1-4/+6
internal_usage is the memory allocated by the current process (intent) while system_usage is the memory allocated globally (actual). Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9774>
2021-05-05gallium/u_threaded: don't set resource pointers to NULL after driver callsMarek Olšák2-51/+89
The pointers won't be used at that point. Just decrement the refcounts. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.eric.pelloux-prayer@amd.com> Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10606>
2021-05-05gallium/u_threaded: rewrite slot layout to reduce wasted spaceMarek Olšák2-460/+448
A lot of space was wasted due to 16-byte alignment for slots. This new layout tries to match glthread. Highlights: - the slot size changed to 8 bytes (was 16), so less padding - the header size changed to 4 bytes (was 8), so some calls can use the remaining 4 bytes in the slot for parameters - draw merging merges up to 307 draws (was 256) due to space savings - parameters in structures are sorted based on implicit type alignment (uint8_t first, pointers last) to make it easier to utilize the 4 bytes after the header and to remove holes - some structures use smaller types for parameters than pipe_context where it's safe (e.g. clear uses float instead of double for depth) Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.eric.pelloux-prayer@amd.com> Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10606>
2021-05-05gallium/u_threaded: handle sampler views == NULL betterMarek Olšák1-4/+7
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.eric.pelloux-prayer@amd.com> Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10606>
2021-05-05gallium/u_threaded: move base_valid_buffer_range to transfer where it belongsMarek Olšák2-16/+17
This saves 8 bytes per resource. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.eric.pelloux-prayer@amd.com> Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10606>
2021-05-05Revert "gallium/u_threaded: align batches and call slots to 16 bytes"Marek Olšák2-12/+3
This reverts commit 3b1ce49bc1e5aff87805b0bab255885c84bf5052. It will be completely rewritten, but let's revert this first. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.eric.pelloux-prayer@amd.com> Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10606>
2021-05-05gallium: Reset attachments to ST_ATTACHMENT_INVALID when revalidatingAdam Jackson1-0/+4
It is *super* *confusing* to leave this initialized to zero, i.e. ST_ATTACHMENT_FRONT_LEFT. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10491>
2021-05-05mesa: Ignore the depth buffer when computing framebuffer floatnessAdam Jackson1-0/+2
Not that Z32F is especially common, but we shouldn't consider it to imply that the color buffers are also float, which is what floatMode is meant to mean. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10491>
2021-05-05mesa: Remove unused _mesa_{create,destroy}_visualAdam Jackson2-72/+7
Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10491>
2021-05-05util/math: change ROUND_DOWN_TO to return a uint64_tSamuel Pitoiset1-2/+2
For 32-bit builds. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Adam Jackson <ajax@redhat.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10622>
2021-05-05intel/genxml: fix raster op fields on gen4/5Dave Airlie3-3/+3
These should be unsigned integers Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10636>
2021-05-05intel/gemxml: move blitter command to render on gen4/5Dave Airlie3-11/+11
The blitter commands don't show up in INTEL_DEBUG=bat, but on gen4/5 they are emitted on the render engine ring so just change the XML to reflect that. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10636>
2021-05-05intel/genxml: rewrite the prefilterop xml to be more consistent.Dave Airlie14-123/+123
This uses a prefix at Ken's suggestion and aligns it across gens Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10636>
2021-05-05intel/genxml: align gen4/5 xml for store data immediateDave Airlie3-6/+3
Just align with the gen6 and later xml Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10636>
2021-05-05intel: fix MI builder for pre-gen7Ilia Mirkin1-0/+4
MI_LOAD_REGISTER_MEM is only available on gen7+, so avoid build errors on earlier generations. Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10636>