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2019-01-29automake: Add include dir for nir src directory19.0-branchpointDylan Baker1-0/+1
Fixes: 6281f26f064ada36b57d45feb68d8e7d783198c9 ("v3d: Add support for shader_image_load_store.") Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2019-01-29automake: Add float64.glsl to dist tarballDylan Baker1-0/+1
Fixes: b63a1f8e40b6705d6a1d806fbd38dcd197d4229b ("glsl: Create file to contain software fp64 functions") Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2019-01-29automake: Fix path to generated sourceDylan Baker1-1/+1
Fixes: b63a1f8e40b6705d6a1d806fbd38dcd197d4229b ("glsl: Create file to contain software fp64 functions") Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2019-01-29nir: Optimize double-precision lower_round_even()Matt Turner1-44/+12
Use the trick of adding and then subtracting 2**52 (52 is the number of explicit mantissa bits a double-precision floating-point value has) to implement round-to-even. Cuts the number of instructions on SKL of the piglit test fs-roundEven-double.shader_test from 109 to 21. Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-01-29ac: use the correct LLVM processor name on Raven2Marek Olšák1-1/+1
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-29v3d: Fix the autotools build.Eric Anholt1-1/+1
Noticed while looking at the gitlab-CI MR.
2019-01-29freedreno: fix sysmem rendering being used when clear is usedJonathan Marek1-1/+1
This batch->cleared value is only used to decide to use sysmem rendering or not, so it should include any buffers that are affected by a clear. This is required because the a2xx fast clear doesn't work with sysmem rendering. The a22x "normal" clear path doesn't work with sysmem either. Signed-off-by: Jonathan Marek <jonathan@marek.ca>
2019-01-29freedreno: fix depth usage logicJonathan Marek1-2/+6
Depth can be used even when there is no restore/resolve of depth. This happens when the depth buffer is invalidated after rendering to avoid the resolve operation. Signed-off-by: Jonathan Marek <jonathan@marek.ca>
2019-01-29freedreno: fix invalidate logicJonathan Marek2-10/+10
Set dirty bits on invalidate to trigger invalidate logic in fd_draw_vbo. Also, resource_written for color needs to be after the invalidate logic. Signed-off-by: Jonathan Marek <jonathan@marek.ca>
2019-01-29mesa/st: wire up DiscardFramebufferJonathan Marek1-0/+25
Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Eric Anholt <eric@anholt.net>
2019-01-29mesa: wire up InvalidateFramebufferRob Clark2-7/+66
And before someone actually starts implementing DiscardFramebuffer() lets rework the interface to something that is actually usable. Signed-off-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2019-01-29st/dri: invalidate_resource depth/stencil before flush_resourceJonathan Marek1-7/+7
This allows freedreno to be aware of the depth invalidate when flushing batches on flush_resource. AFAIK, the only other driver which might care about this change is vc4, where I think it should help by allowing the depth invalidate to work with GALLIUM_HUD. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Eric Anholt <eric@anholt.net>
2019-01-29egl/wayland-drm: Only announce formats via wl_drm which the driver supports.Mario Kleiner5-5/+51
Check if a pixel format is supported by the Wayland servers gpu driver before exposing it to the client via wl_drm, so we avoid reporting formats to the client which the server gpu can't handle. Restrict this reporting to the new color depth 30 formats for now, as the ARGB/XRGB8888 and RGB565 formats are probably supported by every gpu under the sun. Atm. this is mostly useful to allow proper PRIME renderoffload for depth 30 formats on the typical Intel iGPU + NVidia dGPU "NVidia Optimus" laptop combo. Tested on Intel, AMD, NVidia with single-gpu setup and on a Intel + NVidia Optimus setup. Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Reviewed-by: Adam Jackson <ajax@redhat.com> Reviewed-by: Daniel Stone <daniels@collabora.com>
2019-01-29egl/wayland: Allow client->server format conversion for PRIME offload. (v2)Mario Kleiner1-9/+71
Support PRIME render offload between a Wayland server gpu and a Wayland client gpu with different channel ordering for their color formats, e.g., between Intel drivers which currently only support ARGB2101010 and XRGB2101010 import/display and nouveau which only supports ABGR2101010 rendering and display on nv-50 and later. In the wl_visuals table, we also store for each format an alternate sibling format which stores colors at the same precision, but with different channel ordering, e.g., ARGB2101010 <-> ABGR2101010. If a given client-gpu renderable format is not supported by the server for import, but the alternate format is supported by the server, expose the client-gpu renderable format as a valid EGLConfig to the client. At eglSwapBuffers time, during the blitImage() detiling blit from the client backbuffer to the linear buffer, the client format is converted to the server supported format. As we have to do a copy for PRIME anyway, this channel swizzling conversion comes essentially for free. Note that even if a server gpu in principle does support sampling from the clients native format, this conversion will be a performance advantage if it allows to convert to the servers preferred format for direct scanout, as the Wayland compositor may then be able to directly page-flip a fullscreen client wl_buffer onto the primary plane, or onto a hardware overlay plane, avoiding an extra data copy for desktop composition. Tested so far under Weston with: nouveau single-gpu, Intel single-gpu, AMD single-gpu, "Optimus" Intel server iGPU for display + NVidia client dGPU for rendering. v2: Implement minor review comments by Eric Engestrom: Add some comment and assert, and some style fixes for clarity. No functional change. Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Reviewed-by: Adam Jackson <ajax@redhat.com> Reviewed-by: Daniel Stone <daniels@collabora.com>
2019-01-29intel/fs: Use split sends for surface writes on gen9+Jason Ekstrand2-18/+47
Surface reads don't need them because they just have the one address payload. With surface writes, on the other hand, we can put the address and the data in the different halves and avoid building the payload all together. The decrease in register pressure and added freedom in register allocation resulting from this change reduces spilling enough to improve the performance of one customer benchmark by about 2x. Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2019-01-29intel/fs: Add interference between SENDS sourcesJason Ekstrand1-0/+27
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2019-01-29intel/fs: Support SENDS in SHADER_OPCODE_SENDJason Ekstrand3-8/+66
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2019-01-29intel/disasm: Properly disassemble split sendsJason Ekstrand1-19/+142
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2019-01-29intel/eu: Add support for the SENDS[C] messagesJason Ekstrand4-19/+255
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2019-01-29intel/inst: Indent some codeJason Ekstrand1-177/+183
We're about to add some more if cases so let's have the giant re-indent in it's own patch to make review easier. Acked-by: Iago Toral Quiroga <itoral@igalia.com>
2019-01-29intel/inst: Fix the ia16_addr_imm helpersJason Ekstrand1-4/+5
These have clearly never seen any use.... On gen8, the bottom 4 bits are missing so we need to shift them off before we call set_bits and shift again when we get the bits. Found by inspection. Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2019-01-29intel/disasm: Rework SEND decoding to use descriptorsJason Ekstrand1-36/+50
Instead of fetching the information out of the instruction directly, fetch the descriptor and then pluck the information out of the descriptor. The current scheme works ok for SEND but with SENDS, it all falls to pieces because the descriptor is completely shuffled around. This commit doesn't actually convert everything. One notable exception is URB messages which don't even use descriptors in emit_urb_WRITE yet. Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2019-01-29intel/eu: Add more message descriptor helpersJason Ekstrand1-27/+216
We want to be able to extract data from descriptors as well as unify a bit of the descriptor construction. One of the unifications we do is to unify the read/write and dataport descriptors. On gen4-5, read/write are substantially different and the read descriptors change between gen4 and gen4.x. On gen6, they unified layouts between read, write, and dataport. Then, on gen8, they added one bit to the message type field but left it reserved MBZ for read/write messages. This commit chooses to treat that as if they expanded the field everywhere and just didn't have enough enum values for read/write to bother with the extra bit. Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2019-01-29intel/eu/validate: SEND restrictions also apply to SENDCJason Ekstrand1-1/+2
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2019-01-29intel/eu: Use GET_BITS in brw_inst_set_send_ex_descJason Ekstrand1-5/+5
It's a bit more readable Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2019-01-29intel/fs: Use SHADER_OPCODE_SEND for varying UBO pulls on gen7+Jason Ekstrand7-88/+25
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2019-01-29intel/fs: Use SHADER_OPCODE_SEND for texturing on gen7+Jason Ekstrand4-142/+177
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2019-01-29intel/fs: Use a logical opcode for IMAGE_SIZEJason Ekstrand4-6/+21
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2019-01-29intel/fs: Use SHADER_OPCODE_SEND for surface messagesJason Ekstrand5-214/+201
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2019-01-29intel/fs: Add a generic SEND opcodeJason Ekstrand9-3/+91
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2019-01-29intel/eu: Rework surface descriptor helpersJason Ekstrand2-234/+234
This commit pulls the surface descriptor helpers out into brw_eu.h and makes them no longer depend on the codegen infrastructure. This should allow us to use them directly from the IR code instead of the generator. This change is unfortunately less mechanical than perhaps one would like but it should be fairly straightforward. Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2019-01-29intel/eu: Add has_simd4x2 bools to surface_write functionsJason Ekstrand1-6/+8
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2019-01-29intel/fs: Take an explicit exec size in brw_surface_payload_size()Jason Ekstrand1-20/+39
Instead of magically falling back to SIMD8 for atomics and typed messages on Ivy Bridge, explicitly figure out the exec size and pass that into brw_surface_payload_size. Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2019-01-29intel/fs: Handle IMAGE_SIZE in size_read() and is_send_from_grf()Jason Ekstrand1-0/+2
Like all the other sends, it's just mlen * REG_SIZE. Fixes: 3cbc02e4693 "intel: Use TXS for image_size when we have..." Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2019-01-29intel/defines: Explicitly cast to uint32_t in SET_FIELD and SET_BITSJason Ekstrand2-3/+3
If you pass a bool in as the value to set, the C standard says that it gets converted to an int prior to shifting. If you try to set a bool to bit 31, this lands you in undefined behavior. It's better just to add the explicit cast and let the compiler delete it for us. Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2019-01-29intel/fs: Get rid of fs_inst::equalsJason Ekstrand2-23/+7
There are piles of fields that it doesn't check so using it is a lie. The only reason why it's not causing problem is because it has exactly one user which only uses it for MOV instructions (which aren't very interesting) and only on Sandy Bridge and earlier hardware. Just get rid of it and inline it in the one place that it's actually used. Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2019-01-29freedreno: minor cleanupsRob Clark2-2/+0
Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-01-29freedreno: stop frob'ing pipe_resource::nr_samplesRob Clark4-6/+15
Previously we tried to normalize nr_samples to MAX2(1, nr_samples) to avoid having to deal with 0 vs 1 everywhere. But this causes problems in mesa/st, for example st_finalize_texture() will think there is a nr_samples mismatch and recreate the texture. Somehow this manifests as corrupt x11 font rendering on generations that do not support MSAA (but apparently works fine on a5xx and a6xx which do support MSAA.) Fixes: cf0c7258ee0 freedreno/a5xx: MSAA Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-01-29freedreno/a6xx: fix blitter nr_samples checkRob Clark1-1/+3
nr_samples for non-MSAA case could be either zero or one. Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-01-29freedreno/a5xx: fix blitter nr_samples checkRob Clark1-1/+2
nr_samples for non-MSAA case could be either zero or one. Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-01-29radv: Enable VK_EXT_memory_priority.Bas Nieuwenhuizen3-5/+20
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-01-29radv/winsys: Add priority handling during submit.Bas Nieuwenhuizen3-49/+115
Switched to the raw bo list api to avoid having to use 2 arrays for everything. This was introduced in libdrm 2.4.97 which we already depend upon. Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-01-29radv/winsys: Set winsys bo priority on creation.Bas Nieuwenhuizen12-29/+82
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-01-29radv: re-enable fast depth clears for 16-bit surfaces on VISamuel Pitoiset1-8/+0
This has been disabled some months ago because it introduced rendering issues with Shadow Of Warrier II (DXVK). This game is no longer affected, I wonder if 824cfc1ee5e ("radv: rework the TC-compat HTILE hardware bug with COND_EXEC") fixed the problem. I checked The Forest on my Polaris, and it renders fine too. According to Phillip, this gives +5.5% with Rise Of The Tomb Raider and DXVK. This is because DXVK uses 16-bit depth surfaces while the native port from Feral uses 32-bit depth surfaces. Unfortunately, Shadow Of The Tomb Raider isn't affected because it clears each layer of a D16 array texture individually. So it doesn't hit the fast clear path. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-01-28vc4: Enable NEON asm on meson cross-builds.Eric Anholt1-4/+6
The core Mesa with_asm_arch and USE_ARM_ASM flags are disabled for meson cross-builds because of the need to run host binaries on the build system. vc4 doesn't need to do that, so skip with_asm_arch to enable NEON on my cross-builds. Fixes: ebcb4c2156e9 ("meson: Enable VC4's NEON assembly support.")
2019-01-28vc4: Declare the cpu pointers as being modified in NEON asm.Carsten Haitzler (Rasterman)1-18/+15
Otherwise, the compiler is free to reuse the register containing the input for another call and assume that the value hasn't been modified. Fixes crashes on texture upload/download with current gcc. We now have to have a temporary for the cpu2 value, since outputs must be lvalues. (commit message by anholt) Fixes: 4d30024238ef ("vc4: Use NEON to speed up utile loads on Pi2.")
2019-01-28vc4: Use named parameters for the NEON inline asm.Carsten Haitzler (Rasterman)1-80/+100
This makes the asm code more intelligible and clarifies the functional change in the next commit. (commit message and commit squashing by anholt)
2019-01-28kmsro: Add freedreno renderonly supportJonathan Marek4-2/+22
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
2019-01-28freedreno: a2xx: add perfcntrsJonathan Marek8-0/+1118
Based on a5xx perfcntrs implementation. Signed-off-by: Jonathan Marek <jonathan@marek.ca>
2019-01-28freedreno: a2xx: minor solid_vertexbuf fixupsJonathan Marek3-4/+6
The big thing here is the 0x60 offset for the mem2gmem copy which I missed in my last patch. Signed-off-by: Jonathan Marek <jonathan@marek.ca>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-25 18:53:10 +0000