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-rw-r--r--src/freedreno/ir3/ir3.c26
-rw-r--r--src/freedreno/ir3/ir3.h15
-rw-r--r--src/freedreno/ir3/ir3_array_to_ssa.c2
-rw-r--r--src/freedreno/ir3/ir3_compiler_nir.c2
-rw-r--r--src/freedreno/ir3/ir3_context.c6
-rw-r--r--src/freedreno/ir3/ir3_legalize.c20
-rw-r--r--src/freedreno/ir3/ir3_lower_parallelcopy.c20
-rw-r--r--src/freedreno/ir3/ir3_parser.y128
-rw-r--r--src/freedreno/ir3/ir3_ra.c8
9 files changed, 132 insertions, 95 deletions
diff --git a/src/freedreno/ir3/ir3.c b/src/freedreno/ir3/ir3.c
index 14aa704ab75..c42cbf65a5c 100644
--- a/src/freedreno/ir3/ir3.c
+++ b/src/freedreno/ir3/ir3.c
@@ -435,8 +435,11 @@ struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr)
new_instr->regs_count = 0;
for (i = 0; i < instr->regs_count; i++) {
struct ir3_register *reg = instr->regs[i];
- struct ir3_register *new_reg =
- ir3_reg_create(new_instr, reg->num, reg->flags);
+ struct ir3_register *new_reg;
+ if (reg->flags & IR3_REG_DEST)
+ new_reg = ir3_dst_create(new_instr, reg->num, reg->flags);
+ else
+ new_reg = ir3_src_create(new_instr, reg->num, reg->flags);
*new_reg = *reg;
if ((new_reg->flags & IR3_REG_DEST) && new_reg->instr)
new_reg->instr = new_instr;
@@ -456,7 +459,7 @@ void ir3_instr_add_dep(struct ir3_instruction *instr, struct ir3_instruction *de
array_insert(instr, instr->deps, dep);
}
-struct ir3_register * ir3_reg_create(struct ir3_instruction *instr,
+static struct ir3_register * ir3_reg_create(struct ir3_instruction *instr,
int num, int flags)
{
struct ir3 *shader = instr->block->shader;
@@ -468,6 +471,19 @@ struct ir3_register * ir3_reg_create(struct ir3_instruction *instr,
return reg;
}
+struct ir3_register * ir3_src_create(struct ir3_instruction *instr,
+ int num, int flags)
+{
+ assert(!(flags & IR3_REG_DEST));
+ return ir3_reg_create(instr, num, flags);
+}
+
+struct ir3_register * ir3_dst_create(struct ir3_instruction *instr,
+ int num, int flags)
+{
+ return ir3_reg_create(instr, num, flags | IR3_REG_DEST);
+}
+
struct ir3_register * ir3_reg_clone(struct ir3 *shader,
struct ir3_register *reg)
{
@@ -483,7 +499,7 @@ void ir3_reg_set_last_array(struct ir3_instruction *instr,
{
assert(reg->flags & IR3_REG_ARRAY);
assert(reg->flags & IR3_REG_DEST);
- struct ir3_register *new_reg = ir3_reg_create(instr, 0, 0);
+ struct ir3_register *new_reg = ir3_src_create(instr, 0, 0);
*new_reg = *reg;
new_reg->flags &= ~IR3_REG_DEST;
new_reg->def = last_write;
@@ -499,7 +515,7 @@ ir3_instr_set_address(struct ir3_instruction *instr,
debug_assert(instr->block == addr->block);
- instr->address = ir3_reg_create(instr, addr->regs[0]->num,
+ instr->address = ir3_src_create(instr, addr->regs[0]->num,
addr->regs[0]->flags & ~IR3_REG_DEST);
instr->address->def = addr->regs[0];
debug_assert(reg_num(addr->regs[0]) == REG_A0);
diff --git a/src/freedreno/ir3/ir3.h b/src/freedreno/ir3/ir3.h
index cb82eede37c..04956d597b5 100644
--- a/src/freedreno/ir3/ir3.h
+++ b/src/freedreno/ir3/ir3.h
@@ -604,7 +604,9 @@ struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr);
void ir3_instr_add_dep(struct ir3_instruction *instr, struct ir3_instruction *dep);
const char *ir3_instr_name(struct ir3_instruction *instr);
-struct ir3_register * ir3_reg_create(struct ir3_instruction *instr,
+struct ir3_register * ir3_src_create(struct ir3_instruction *instr,
+ int num, int flags);
+struct ir3_register * ir3_dst_create(struct ir3_instruction *instr,
int num, int flags);
struct ir3_register * ir3_reg_clone(struct ir3 *shader,
struct ir3_register *reg);
@@ -1517,7 +1519,7 @@ static inline struct ir3_register * __ssa_src(struct ir3_instruction *instr,
struct ir3_register *reg;
if (src->regs[0]->flags & IR3_REG_HALF)
flags |= IR3_REG_HALF;
- reg = ir3_reg_create(instr, INVALID_REG, IR3_REG_SSA | flags);
+ reg = ir3_src_create(instr, INVALID_REG, IR3_REG_SSA | flags);
reg->def = src->regs[0];
reg->wrmask = src->regs[0]->wrmask;
return reg;
@@ -1525,8 +1527,7 @@ static inline struct ir3_register * __ssa_src(struct ir3_instruction *instr,
static inline struct ir3_register * __ssa_dst(struct ir3_instruction *instr)
{
- struct ir3_register *reg = ir3_reg_create(instr, INVALID_REG, 0);
- reg->flags |= IR3_REG_SSA | IR3_REG_DEST;
+ struct ir3_register *reg = ir3_dst_create(instr, INVALID_REG, IR3_REG_SSA);
reg->instr = instr;
return reg;
}
@@ -1541,7 +1542,7 @@ create_immed_typed(struct ir3_block *block, uint32_t val, type_t type)
mov->cat1.src_type = type;
mov->cat1.dst_type = type;
__ssa_dst(mov)->flags |= flags;
- ir3_reg_create(mov, 0, IR3_REG_IMMED | flags)->uim_val = val;
+ ir3_src_create(mov, 0, IR3_REG_IMMED | flags)->uim_val = val;
return mov;
}
@@ -1562,7 +1563,7 @@ create_uniform_typed(struct ir3_block *block, unsigned n, type_t type)
mov->cat1.src_type = type;
mov->cat1.dst_type = type;
__ssa_dst(mov)->flags |= flags;
- ir3_reg_create(mov, n, IR3_REG_CONST | flags);
+ ir3_src_create(mov, n, IR3_REG_CONST | flags);
return mov;
}
@@ -1583,7 +1584,7 @@ create_uniform_indirect(struct ir3_block *block, int n, type_t type,
mov->cat1.src_type = type;
mov->cat1.dst_type = type;
__ssa_dst(mov);
- ir3_reg_create(mov, 0, IR3_REG_CONST | IR3_REG_RELATIV)->array.offset = n;
+ ir3_src_create(mov, 0, IR3_REG_CONST | IR3_REG_RELATIV)->array.offset = n;
ir3_instr_set_address(mov, address);
diff --git a/src/freedreno/ir3/ir3_array_to_ssa.c b/src/freedreno/ir3/ir3_array_to_ssa.c
index af0a86be3cb..d515f0a8cd5 100644
--- a/src/freedreno/ir3/ir3_array_to_ssa.c
+++ b/src/freedreno/ir3/ir3_array_to_ssa.c
@@ -118,7 +118,7 @@ read_value_beginning(struct array_ctx *ctx, struct ir3_block *block, struct ir3_
if (src) {
src_reg = __ssa_src(phi, src->instr, flags);
} else {
- src_reg = ir3_reg_create(phi, INVALID_REG, flags | IR3_REG_SSA);
+ src_reg = ir3_src_create(phi, INVALID_REG, flags | IR3_REG_SSA);
}
src_reg->array.id = arr->id;
src_reg->size = arr->length;
diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c
index d27a6fceb73..087f191044f 100644
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -2791,7 +2791,7 @@ resolve_phis(struct ir3_context *ctx, struct ir3_block *block)
if (get_block(ctx, nsrc->pred) == pred) {
if (nsrc->src.ssa->parent_instr->type == nir_instr_type_ssa_undef) {
/* Create an ir3 undef */
- ir3_reg_create(phi, INVALID_REG, phi->regs[0]->flags & ~IR3_REG_DEST);
+ ir3_src_create(phi, INVALID_REG, phi->regs[0]->flags & ~IR3_REG_DEST);
} else {
struct ir3_instruction *src = ir3_get_src(ctx, &nsrc->src)[0];
__ssa_src(phi, src, 0);
diff --git a/src/freedreno/ir3/ir3_context.c b/src/freedreno/ir3/ir3_context.c
index 1a92497cdf3..954dd10979b 100644
--- a/src/freedreno/ir3/ir3_context.c
+++ b/src/freedreno/ir3/ir3_context.c
@@ -584,7 +584,7 @@ ir3_create_array_load(struct ir3_context *ctx, struct ir3_array *arr, int n,
mov->barrier_class = IR3_BARRIER_ARRAY_R;
mov->barrier_conflict = IR3_BARRIER_ARRAY_W;
__ssa_dst(mov)->flags |= flags;
- src = ir3_reg_create(mov, 0, IR3_REG_ARRAY |
+ src = ir3_src_create(mov, 0, IR3_REG_ARRAY |
COND(address, IR3_REG_RELATIV) | flags);
src->def = (arr->last_write && arr->last_write->instr->block == block) ?
arr->last_write : NULL;
@@ -648,7 +648,7 @@ ir3_create_array_store(struct ir3_context *ctx, struct ir3_array *arr, int n,
}
mov->barrier_class = IR3_BARRIER_ARRAY_W;
mov->barrier_conflict = IR3_BARRIER_ARRAY_R | IR3_BARRIER_ARRAY_W;
- dst = ir3_reg_create(mov, 0, IR3_REG_DEST | IR3_REG_SSA | IR3_REG_ARRAY |
+ dst = ir3_dst_create(mov, 0, IR3_REG_SSA | IR3_REG_ARRAY |
flags |
COND(address, IR3_REG_RELATIV));
dst->instr = mov;
@@ -656,7 +656,7 @@ ir3_create_array_store(struct ir3_context *ctx, struct ir3_array *arr, int n,
dst->array.id = arr->id;
dst->array.offset = n;
dst->array.base = INVALID_REG;
- ir3_reg_create(mov, 0, IR3_REG_SSA | flags)->def = src->regs[0];
+ ir3_src_create(mov, 0, IR3_REG_SSA | flags)->def = src->regs[0];
if (arr->last_write && arr->last_write->instr->block == block)
ir3_reg_set_last_array(mov, dst, arr->last_write);
diff --git a/src/freedreno/ir3/ir3_legalize.c b/src/freedreno/ir3/ir3_legalize.c
index e48fd8be2da..f1deae88b5a 100644
--- a/src/freedreno/ir3/ir3_legalize.c
+++ b/src/freedreno/ir3/ir3_legalize.c
@@ -314,9 +314,9 @@ legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block)
/* (ss)bary.f (ei)r63.x, 0, r0.x */
baryf = ir3_instr_create(block, OPC_BARY_F, 3);
- ir3_reg_create(baryf, regid(63, 0), 0);
- ir3_reg_create(baryf, 0, IR3_REG_IMMED)->iim_val = 0;
- ir3_reg_create(baryf, regid(0, 0), 0);
+ ir3_dst_create(baryf, regid(63, 0), 0);
+ ir3_src_create(baryf, 0, IR3_REG_IMMED)->iim_val = 0;
+ ir3_src_create(baryf, regid(0, 0), 0);
last_input = baryf;
}
@@ -344,9 +344,9 @@ legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block)
/* (ss)bary.f (ei)r63.x, 0, r0.x */
baryf = ir3_instr_create(block, OPC_BARY_F, 3);
- ir3_reg_create(baryf, regid(63, 0), 0)->flags |= IR3_REG_EI;
- ir3_reg_create(baryf, 0, IR3_REG_IMMED)->iim_val = 0;
- ir3_reg_create(baryf, regid(0, 0), 0);
+ ir3_dst_create(baryf, regid(63, 0), 0)->flags |= IR3_REG_EI;
+ ir3_src_create(baryf, 0, IR3_REG_IMMED)->iim_val = 0;
+ ir3_src_create(baryf, regid(0, 0), 0);
/* insert the dummy bary.f at head: */
list_delinit(&baryf->node);
@@ -628,15 +628,15 @@ block_sched(struct ir3 *ir)
* frequently/always end up being a fall-thru):
*/
br = ir3_instr_create(block, OPC_B, 2);
- ir3_reg_create(br, INVALID_REG, IR3_REG_DEST);
- ir3_reg_create(br, regid(REG_P0, 0), 0)->def = block->condition->regs[0];
+ ir3_dst_create(br, INVALID_REG, 0);
+ ir3_src_create(br, regid(REG_P0, 0), 0)->def = block->condition->regs[0];
br->cat0.inv1 = true;
br->cat0.target = block->successors[1];
/* "then" branch: */
br = ir3_instr_create(block, OPC_B, 2);
- ir3_reg_create(br, INVALID_REG, IR3_REG_DEST);
- ir3_reg_create(br, regid(REG_P0, 0), 0)->def = block->condition->regs[0];
+ ir3_dst_create(br, INVALID_REG, 0);
+ ir3_src_create(br, regid(REG_P0, 0), 0)->def = block->condition->regs[0];
br->cat0.target = block->successors[0];
} else if (block->successors[0]) {
diff --git a/src/freedreno/ir3/ir3_lower_parallelcopy.c b/src/freedreno/ir3/ir3_lower_parallelcopy.c
index 0fa5e765210..f0716e2daac 100644
--- a/src/freedreno/ir3/ir3_lower_parallelcopy.c
+++ b/src/freedreno/ir3/ir3_lower_parallelcopy.c
@@ -72,11 +72,11 @@ static void
do_xor(struct ir3_instruction *instr, unsigned dst_num, unsigned src1_num, unsigned src2_num, unsigned flags)
{
struct ir3_instruction *xor = ir3_instr_create(instr->block, OPC_XOR_B, 3);
- struct ir3_register *dst = ir3_reg_create(xor, dst_num, flags | IR3_REG_DEST);
+ struct ir3_register *dst = ir3_dst_create(xor, dst_num, flags);
dst->wrmask = 1;
- struct ir3_register *src1 = ir3_reg_create(xor, src1_num, flags);
+ struct ir3_register *src1 = ir3_src_create(xor, src1_num, flags);
src1->wrmask = 1;
- struct ir3_register *src2 = ir3_reg_create(xor, src2_num, flags);
+ struct ir3_register *src2 = ir3_src_create(xor, src2_num, flags);
src2->wrmask = 1;
ir3_instr_move_before(xor, instr);
@@ -187,17 +187,17 @@ do_copy(struct ir3_instruction *instr, const struct copy_entry *entry)
if (entry->src.reg % 2 == 0) {
/* cov.u32u16 dst, src */
struct ir3_instruction *cov = ir3_instr_create(instr->block, OPC_MOV, 2);
- ir3_reg_create(cov, dst_num, entry->flags | IR3_REG_DEST)->wrmask = 1;
- ir3_reg_create(cov, src_num, entry->flags & ~IR3_REG_HALF)->wrmask = 1;
+ ir3_dst_create(cov, dst_num, entry->flags)->wrmask = 1;
+ ir3_src_create(cov, src_num, entry->flags & ~IR3_REG_HALF)->wrmask = 1;
cov->cat1.dst_type = TYPE_U16;
cov->cat1.src_type = TYPE_U32;
ir3_instr_move_before(cov, instr);
} else {
/* shr.b dst, src, h(16) */
struct ir3_instruction *shr = ir3_instr_create(instr->block, OPC_SHR_B, 3);
- ir3_reg_create(shr, dst_num, entry->flags | IR3_REG_DEST)->wrmask = 1;
- ir3_reg_create(shr, src_num, entry->flags & ~IR3_REG_HALF)->wrmask = 1;
- ir3_reg_create(shr, 0, entry->flags | IR3_REG_IMMED)->uim_val = 16;
+ ir3_dst_create(shr, dst_num, entry->flags)->wrmask = 1;
+ ir3_src_create(shr, src_num, entry->flags & ~IR3_REG_HALF)->wrmask = 1;
+ ir3_src_create(shr, 0, entry->flags | IR3_REG_IMMED)->uim_val = 16;
ir3_instr_move_before(shr, instr);
}
return;
@@ -208,8 +208,8 @@ do_copy(struct ir3_instruction *instr, const struct copy_entry *entry)
unsigned dst_num = ra_physreg_to_num(entry->dst, entry->flags);
struct ir3_instruction *mov = ir3_instr_create(instr->block, OPC_MOV, 2);
- ir3_reg_create(mov, dst_num, entry->flags | IR3_REG_DEST)->wrmask = 1;
- ir3_reg_create(mov, src_num, entry->flags | entry->src.flags)->wrmask = 1;
+ ir3_dst_create(mov, dst_num, entry->flags)->wrmask = 1;
+ ir3_src_create(mov, src_num, entry->flags | entry->src.flags)->wrmask = 1;
mov->cat1.dst_type = (entry->flags & IR3_REG_HALF) ? TYPE_U16 : TYPE_U32;
mov->cat1.src_type = (entry->flags & IR3_REG_HALF) ? TYPE_U16 : TYPE_U32;
if (entry->src.flags & IR3_REG_IMMED)
diff --git a/src/freedreno/ir3/ir3_parser.y b/src/freedreno/ir3/ir3_parser.y
index 6609f216b6a..931520adfe4 100644
--- a/src/freedreno/ir3/ir3_parser.y
+++ b/src/freedreno/ir3/ir3_parser.y
@@ -152,13 +152,25 @@ static struct ir3_instruction * parse_type_type(struct ir3_instruction *instr,
return instr;
}
-static struct ir3_register * new_reg(int num, unsigned flags)
+static struct ir3_register * new_src(int num, unsigned flags)
{
struct ir3_register *reg;
flags |= rflags.flags;
if (num & 0x1)
flags |= IR3_REG_HALF;
- reg = ir3_reg_create(instr, num>>1, flags);
+ reg = ir3_src_create(instr, num>>1, flags);
+ reg->wrmask = MAX2(1, rflags.wrmask);
+ rflags.flags = rflags.wrmask = 0;
+ return reg;
+}
+
+static struct ir3_register * new_dst(int num, unsigned flags)
+{
+ struct ir3_register *reg;
+ flags |= rflags.flags;
+ if (num & 0x1)
+ flags |= IR3_REG_HALF;
+ reg = ir3_dst_create(instr, num>>1, flags);
reg->wrmask = MAX2(1, rflags.wrmask);
rflags.flags = rflags.wrmask = 0;
return reg;
@@ -166,7 +178,7 @@ static struct ir3_register * new_reg(int num, unsigned flags)
static struct ir3_register * dummy_dst(void)
{
- return new_reg(0, 0);
+ return new_dst(0, 0);
}
static void fixup_cat5_s2en(void)
@@ -609,7 +621,7 @@ static void print_token(FILE *file, int type, YYSTYPE value)
%type <num> integer offset
%type <num> flut_immed
%type <flt> float
-%type <reg> reg const
+%type <reg> src dst const
%type <tok> cat1_opc
%type <tok> cat2_opc_1src cat2_opc_2src_cnd cat2_opc_2src
%type <tok> cat3_opc
@@ -784,14 +796,14 @@ cat1_mova1: T_OP_MOVA1 T_A1 ',' {
new_instr(OPC_MOV);
instr->cat1.src_type = TYPE_U16;
instr->cat1.dst_type = TYPE_U16;
- new_reg((61 << 3) + 2, IR3_REG_HALF);
+ new_dst((61 << 3) + 2, IR3_REG_HALF);
} cat1_src
cat1_mova: T_OP_MOVA T_A0 ',' {
new_instr(OPC_MOV);
instr->cat1.src_type = TYPE_S16;
instr->cat1.dst_type = TYPE_S16;
- new_reg((61 << 3), IR3_REG_HALF);
+ new_dst((61 << 3), IR3_REG_HALF);
} cat1_src
cat1_swz: T_OP_SWZ '.' T_CAT1_TYPE_TYPE { parse_type_type(new_instr(OPC_SWZ), $3); } dst_reg ',' dst_reg ',' src_reg ',' src_reg
@@ -808,7 +820,7 @@ cat1_instr: cat1_movmsk
| cat1_gat
| cat1_sct
| cat1_opc dst_reg ',' cat1_src
-| cat1_opc relative_gpr ',' cat1_src
+| cat1_opc relative_gpr_dst ',' cat1_src
cat2_opc_1src: T_OP_ABSNEG_F { new_instr(OPC_ABSNEG_F); }
| T_OP_ABSNEG_S { new_instr(OPC_ABSNEG_S); }
@@ -973,25 +985,25 @@ cat6_dim: '.' T_1D { instr->cat6.d = 1; }
| '.' T_4D { instr->cat6.d = 4; }
cat6_type: '.' type { instr->cat6.type = $2; }
-cat6_offset: offset { new_reg(0, IR3_REG_IMMED)->iim_val = $1; }
-| '+' reg
+cat6_offset: offset { new_src(0, IR3_REG_IMMED)->iim_val = $1; }
+| '+' src
cat6_dst_offset: offset { instr->cat6.dst_offset = $1; }
-| '+' reg { instr->flags |= IR3_INSTR_G; }
+| '+' src { instr->flags |= IR3_INSTR_G; }
cat6_immed: integer { instr->cat6.iim_val = $1; }
-cat6_load: T_OP_LDG { new_instr(OPC_LDG); } cat6_type dst_reg ',' 'g' '[' reg cat6_offset ']' ',' immediate
-| T_OP_LDP { new_instr(OPC_LDP); } cat6_type dst_reg ',' 'p' '[' reg cat6_offset ']' ',' immediate
-| T_OP_LDL { new_instr(OPC_LDL); } cat6_type dst_reg ',' 'l' '[' reg cat6_offset ']' ',' immediate
-| T_OP_LDLW { new_instr(OPC_LDLW); } cat6_type dst_reg ',' 'l' '[' reg cat6_offset ']' ',' immediate
+cat6_load: T_OP_LDG { new_instr(OPC_LDG); } cat6_type dst_reg ',' 'g' '[' src cat6_offset ']' ',' immediate
+| T_OP_LDP { new_instr(OPC_LDP); } cat6_type dst_reg ',' 'p' '[' src cat6_offset ']' ',' immediate
+| T_OP_LDL { new_instr(OPC_LDL); } cat6_type dst_reg ',' 'l' '[' src cat6_offset ']' ',' immediate
+| T_OP_LDLW { new_instr(OPC_LDLW); } cat6_type dst_reg ',' 'l' '[' src cat6_offset ']' ',' immediate
| T_OP_LDLV { new_instr(OPC_LDLV); } cat6_type dst_reg ',' 'l' '[' integer ']' {
- new_reg(0, IR3_REG_IMMED)->iim_val = $8;
+ new_src(0, IR3_REG_IMMED)->iim_val = $8;
} ',' immediate
// TODO some of the cat6 instructions have different syntax for a6xx..
//| T_OP_LDIB { new_instr(OPC_LDIB); } cat6_type dst_reg cat6_offset ',' reg ',' cat6_immed
-cat6_store: T_OP_STG { new_instr(OPC_STG); dummy_dst(); } cat6_type 'g' '[' reg cat6_dst_offset ']' ',' reg ',' immediate {
+cat6_store: T_OP_STG { new_instr(OPC_STG); dummy_dst(); } cat6_type 'g' '[' src cat6_dst_offset ']' ',' src ',' immediate {
/* fixup src order, the offset reg is expected last currently */
if (instr->flags & IR3_INSTR_G) {
struct ir3_register *offset = instr->regs[2];
@@ -1000,13 +1012,13 @@ cat6_store: T_OP_STG { new_instr(OPC_STG); dummy_dst(); } cat6_type 'g'
instr->regs[4] = offset;
}
}
-| T_OP_STP { new_instr(OPC_STP); dummy_dst(); } cat6_type 'p' '[' reg cat6_dst_offset ']' ',' reg ',' immediate
-| T_OP_STL { new_instr(OPC_STL); dummy_dst(); } cat6_type 'l' '[' reg cat6_dst_offset ']' ',' reg ',' immediate
-| T_OP_STLW { new_instr(OPC_STLW); dummy_dst(); } cat6_type 'l' '[' reg cat6_dst_offset ']' ',' reg ',' immediate
+| T_OP_STP { new_instr(OPC_STP); dummy_dst(); } cat6_type 'p' '[' src cat6_dst_offset ']' ',' src ',' immediate
+| T_OP_STL { new_instr(OPC_STL); dummy_dst(); } cat6_type 'l' '[' src cat6_dst_offset ']' ',' src ',' immediate
+| T_OP_STLW { new_instr(OPC_STLW); dummy_dst(); } cat6_type 'l' '[' src cat6_dst_offset ']' ',' src ',' immediate
-cat6_storeib: T_OP_STIB { new_instr(OPC_STIB); dummy_dst(); } cat6_typed cat6_dim cat6_type '.' cat6_immed'g' '[' immediate ']' ',' reg ',' reg ',' reg
+cat6_storeib: T_OP_STIB { new_instr(OPC_STIB); dummy_dst(); } cat6_typed cat6_dim cat6_type '.' cat6_immed'g' '[' immediate ']' ',' src ',' src ',' src
-cat6_prefetch: T_OP_PREFETCH { new_instr(OPC_PREFETCH); new_reg(0,0); /* dummy dst */ } 'g' '[' reg cat6_offset ']' ',' cat6_immed
+cat6_prefetch: T_OP_PREFETCH { new_instr(OPC_PREFETCH); new_dst(0,0); /* dummy dst */ } 'g' '[' src cat6_offset ']' ',' cat6_immed
cat6_atomic_opc: T_OP_ATOMIC_ADD { new_instr(OPC_ATOMIC_ADD); }
| T_OP_ATOMIC_SUB { new_instr(OPC_ATOMIC_SUB); }
@@ -1020,11 +1032,11 @@ cat6_atomic_opc: T_OP_ATOMIC_ADD { new_instr(OPC_ATOMIC_ADD); }
| T_OP_ATOMIC_OR { new_instr(OPC_ATOMIC_OR); }
| T_OP_ATOMIC_XOR { new_instr(OPC_ATOMIC_XOR); }
-cat6_atomic_g: cat6_atomic_opc cat6_typed cat6_dim cat6_type '.' cat6_immed '.' 'g' dst_reg ',' 'g' '[' cat6_reg_or_immed ']' ',' reg ',' reg ',' reg {
+cat6_atomic_g: cat6_atomic_opc cat6_typed cat6_dim cat6_type '.' cat6_immed '.' 'g' dst_reg ',' 'g' '[' cat6_reg_or_immed ']' ',' src ',' src ',' src {
instr->flags |= IR3_INSTR_G;
}
-cat6_atomic_l: cat6_atomic_opc cat6_typed cat6_dim cat6_type '.' cat6_immed '.' 'l' dst_reg ',' 'l' '[' cat6_reg_or_immed ']' ',' reg
+cat6_atomic_l: cat6_atomic_opc cat6_typed cat6_dim cat6_type '.' cat6_immed '.' 'l' dst_reg ',' 'l' '[' cat6_reg_or_immed ']' ',' src
cat6_atomic: cat6_atomic_g
| cat6_atomic_l
@@ -1035,8 +1047,8 @@ cat6_ibo_opc_ldgb: T_OP_LDGB { new_instr(OPC_LDGB); }
cat6_ibo_opc_stgb: T_OP_STGB { new_instr(OPC_STGB); }
cat6_ibo: cat6_ibo_opc_1src cat6_type cat6_dim dst_reg ',' 'g' '[' cat6_reg_or_immed ']'
-| cat6_ibo_opc_ldgb cat6_typed cat6_dim cat6_type '.' cat6_immed dst_reg ',' 'g' '[' cat6_reg_or_immed ']' ',' reg ',' reg
-| cat6_ibo_opc_stgb cat6_typed cat6_dim cat6_type '.' cat6_immed { dummy_dst(); } 'g' '[' cat6_reg_or_immed ']' ',' reg ',' cat6_reg_or_immed ',' reg
+| cat6_ibo_opc_ldgb cat6_typed cat6_dim cat6_type '.' cat6_immed dst_reg ',' 'g' '[' cat6_reg_or_immed ']' ',' src ',' src
+| cat6_ibo_opc_stgb cat6_typed cat6_dim cat6_type '.' cat6_immed { dummy_dst(); } 'g' '[' cat6_reg_or_immed ']' ',' src ',' cat6_reg_or_immed ',' src
cat6_id_opc:
T_OP_GETSPID { new_instr(OPC_GETSPID); }
@@ -1051,8 +1063,8 @@ cat6_bindless_mode: T_IMM cat6_bindless_base
| T_UNIFORM cat6_bindless_base
| T_NONUNIFORM cat6_bindless_base { instr->flags |= IR3_INSTR_NONUNIF; }
-cat6_reg_or_immed: reg
-| integer { new_reg(0, IR3_REG_IMMED)->iim_val = $1; }
+cat6_reg_or_immed: src
+| integer { new_src(0, IR3_REG_IMMED)->iim_val = $1; }
cat6_bindless_ibo_opc_1src: T_OP_RESINFO_B { new_instr(OPC_RESINFO); }
@@ -1119,12 +1131,17 @@ cat7_barrier: T_OP_BAR { new_instr(OPC_BAR); } cat7_scopes
cat7_instr: cat7_barrier
-reg: T_REGISTER { $$ = new_reg($1, 0); }
-| T_A0 { $$ = new_reg((61 << 3), IR3_REG_HALF); }
-| T_A1 { $$ = new_reg((61 << 3) + 1, IR3_REG_HALF); }
-| T_P0 { $$ = new_reg((62 << 3) + $1, 0); }
+src: T_REGISTER { $$ = new_src($1, 0); }
+| T_A0 { $$ = new_src((61 << 3), IR3_REG_HALF); }
+| T_A1 { $$ = new_src((61 << 3) + 1, IR3_REG_HALF); }
+| T_P0 { $$ = new_src((62 << 3) + $1, 0); }
+
+dst: T_REGISTER { $$ = new_dst($1, 0); }
+| T_A0 { $$ = new_dst((61 << 3), IR3_REG_HALF); }
+| T_A1 { $$ = new_dst((61 << 3) + 1, IR3_REG_HALF); }
+| T_P0 { $$ = new_dst((62 << 3) + $1, 0); }
-const: T_CONSTANT { $$ = new_reg($1, IR3_REG_CONST); }
+const: T_CONSTANT { $$ = new_src($1, IR3_REG_CONST); }
dst_reg_flag: T_EVEN { instr->cat1.round = ROUND_EVEN; }
| T_POS_INFINITY { instr->cat1.round = ROUND_POS_INF; }
@@ -1136,8 +1153,8 @@ dst_reg_flags: dst_reg_flag
| dst_reg_flag dst_reg_flags
/* note: destination registers are always incremented in repeat */
-dst_reg: reg { $1->flags |= IR3_REG_R; }
-| dst_reg_flags reg { $2->flags |= IR3_REG_R; }
+dst_reg: dst { $1->flags |= IR3_REG_R; }
+| dst_reg_flags dst { $2->flags |= IR3_REG_R; }
src_reg_flag: T_ABSNEG { rflags.flags |= IR3_REG_ABS|IR3_REG_NEGATE; }
| T_NEG { rflags.flags |= IR3_REG_NEGATE; }
@@ -1147,8 +1164,8 @@ src_reg_flag: T_ABSNEG { rflags.flags |= IR3_REG_ABS|IR3_REG_NEGATE;
src_reg_flags: src_reg_flag
| src_reg_flag src_reg_flags
-src_reg: reg
-| src_reg_flags reg
+src_reg: src
+| src_reg_flags src
src_const: const
| src_reg_flags const
@@ -1168,32 +1185,35 @@ offset: { $$ = 0; }
| '+' integer { $$ = $2; }
| '-' integer { $$ = -$2; }
-relative_gpr: 'r' '<' T_A0 offset '>' { new_reg(0, IR3_REG_RELATIV)->array.offset = $4; }
-| T_HR '<' T_A0 offset '>' { new_reg(0, IR3_REG_RELATIV | IR3_REG_HALF)->array.offset = $4; }
+relative_gpr_src: 'r' '<' T_A0 offset '>' { new_src(0, IR3_REG_RELATIV)->array.offset = $4; }
+| T_HR '<' T_A0 offset '>' { new_src(0, IR3_REG_RELATIV | IR3_REG_HALF)->array.offset = $4; }
+
+relative_gpr_dst: 'r' '<' T_A0 offset '>' { new_dst(0, IR3_REG_RELATIV)->array.offset = $4; }
+| T_HR '<' T_A0 offset '>' { new_dst(0, IR3_REG_RELATIV | IR3_REG_HALF)->array.offset = $4; }
-relative_const: 'c' '<' T_A0 offset '>' { new_reg(0, IR3_REG_RELATIV | IR3_REG_CONST)->array.offset = $4; }
-| T_HC '<' T_A0 offset '>' { new_reg(0, IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_HALF)->array.offset = $4; }
+relative_const: 'c' '<' T_A0 offset '>' { new_src(0, IR3_REG_RELATIV | IR3_REG_CONST)->array.offset = $4; }
+| T_HC '<' T_A0 offset '>' { new_src(0, IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_HALF)->array.offset = $4; }
-relative: relative_gpr
+relative: relative_gpr_src
| relative_const
/* cat1 immediates differ slighly in the floating point case from the cat2
* case which can only encode certain predefined values (ie. and index into
* the FLUT table)
*/
-immediate_cat1: integer { new_reg(0, IR3_REG_IMMED)->iim_val = type_size(instr->cat1.src_type) < 32 ? $1 & 0xffff : $1; }
-| '(' integer ')' { new_reg(0, IR3_REG_IMMED)->fim_val = $2; }
-| '(' float ')' { new_reg(0, IR3_REG_IMMED)->fim_val = $2; }
-| 'h' '(' integer ')' { new_reg(0, IR3_REG_IMMED | IR3_REG_HALF)->iim_val = $3 & 0xffff; }
-| 'h' '(' float ')' { new_reg(0, IR3_REG_IMMED | IR3_REG_HALF)->uim_val = _mesa_float_to_half($3); }
-| '(' T_NAN ')' { new_reg(0, IR3_REG_IMMED)->fim_val = NAN; }
-| '(' T_INF ')' { new_reg(0, IR3_REG_IMMED)->fim_val = INFINITY; }
-
-immediate: integer { new_reg(0, IR3_REG_IMMED)->iim_val = $1; }
-| '(' integer ')' { new_reg(0, IR3_REG_IMMED)->fim_val = $2; }
-| flut_immed { new_reg(0, IR3_REG_IMMED)->uim_val = $1; }
-| 'h' '(' integer ')' { new_reg(0, IR3_REG_IMMED | IR3_REG_HALF)->iim_val = $3; }
-| 'h' flut_immed { new_reg(0, IR3_REG_IMMED | IR3_REG_HALF)->uim_val = $2; }
+immediate_cat1: integer { new_src(0, IR3_REG_IMMED)->iim_val = type_size(instr->cat1.src_type) < 32 ? $1 & 0xffff : $1; }
+| '(' integer ')' { new_src(0, IR3_REG_IMMED)->fim_val = $2; }
+| '(' float ')' { new_src(0, IR3_REG_IMMED)->fim_val = $2; }
+| 'h' '(' integer ')' { new_src(0, IR3_REG_IMMED | IR3_REG_HALF)->iim_val = $3 & 0xffff; }
+| 'h' '(' float ')' { new_src(0, IR3_REG_IMMED | IR3_REG_HALF)->uim_val = _mesa_float_to_half($3); }
+| '(' T_NAN ')' { new_src(0, IR3_REG_IMMED)->fim_val = NAN; }
+| '(' T_INF ')' { new_src(0, IR3_REG_IMMED)->fim_val = INFINITY; }
+
+immediate: integer { new_src(0, IR3_REG_IMMED)->iim_val = $1; }
+| '(' integer ')' { new_src(0, IR3_REG_IMMED)->fim_val = $2; }
+| flut_immed { new_src(0, IR3_REG_IMMED)->uim_val = $1; }
+| 'h' '(' integer ')' { new_src(0, IR3_REG_IMMED | IR3_REG_HALF)->iim_val = $3; }
+| 'h' flut_immed { new_src(0, IR3_REG_IMMED | IR3_REG_HALF)->uim_val = $2; }
/* Float LUT values accepted as immed: */
flut_immed: T_FLUT_0_0
diff --git a/src/freedreno/ir3/ir3_ra.c b/src/freedreno/ir3/ir3_ra.c
index eb53d65fb1b..557d3cdf5ee 100644
--- a/src/freedreno/ir3/ir3_ra.c
+++ b/src/freedreno/ir3/ir3_ra.c
@@ -1166,7 +1166,7 @@ insert_parallel_copy_instr(struct ra_ctx *ctx, struct ir3_instruction *instr)
for (unsigned i = 0; i < ctx->parallel_copies_count; i++) {
struct ra_parallel_copy *entry = &ctx->parallel_copies[i];
struct ir3_register *reg =
- ir3_reg_create(pcopy, INVALID_REG,
+ ir3_dst_create(pcopy, INVALID_REG,
entry->interval->interval.reg->flags & ~IR3_REG_SSA);
reg->size = entry->interval->interval.reg->size;
reg->wrmask = entry->interval->interval.reg->wrmask;
@@ -1176,7 +1176,7 @@ insert_parallel_copy_instr(struct ra_ctx *ctx, struct ir3_instruction *instr)
for (unsigned i = 0; i < ctx->parallel_copies_count; i++) {
struct ra_parallel_copy *entry = &ctx->parallel_copies[i];
struct ir3_register *reg =
- ir3_reg_create(pcopy, INVALID_REG,
+ ir3_src_create(pcopy, INVALID_REG,
entry->interval->interval.reg->flags & ~(IR3_REG_DEST | IR3_REG_SSA));
reg->size = entry->interval->interval.reg->size;
reg->wrmask = entry->interval->interval.reg->wrmask;
@@ -1611,7 +1611,7 @@ insert_liveout_copy(struct ir3_block *block, physreg_t dst, physreg_t src,
}
struct ir3_register *dst_reg =
- ir3_reg_create(pcopy, INVALID_REG,
+ ir3_dst_create(pcopy, INVALID_REG,
reg->flags & ~IR3_REG_SSA);
dst_reg->wrmask = reg->wrmask;
dst_reg->size = reg->size;
@@ -1622,7 +1622,7 @@ insert_liveout_copy(struct ir3_block *block, physreg_t dst, physreg_t src,
}
struct ir3_register *src_reg =
- ir3_reg_create(pcopy, INVALID_REG, reg->flags & ~(IR3_REG_DEST | IR3_REG_SSA));
+ ir3_src_create(pcopy, INVALID_REG, reg->flags & ~(IR3_REG_DEST | IR3_REG_SSA));
src_reg->wrmask = reg->wrmask;
src_reg->size = reg->size;
assign_reg(pcopy, src_reg, ra_physreg_to_num(src, reg->flags));
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-19 12:58:42 +0000