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-rw-r--r--src/mesa/drivers/dri/i965/brw_defines.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index b2ce197faba..bd7d0b1c9a7 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1031,6 +1031,15 @@ enum opcode {
SHADER_OPCODE_GEN4_SCRATCH_WRITE,
SHADER_OPCODE_GEN7_SCRATCH_READ,
+ /**
+ * Gen8+ SIMD8 URB Read message.
+ *
+ * Source 0: The header register, containing URB handles (g1).
+ *
+ * Currently only supports constant offsets, in inst->offset.
+ */
+ SHADER_OPCODE_URB_READ_SIMD8,
+
SHADER_OPCODE_URB_WRITE_SIMD8,
SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT,
SHADER_OPCODE_URB_WRITE_SIMD8_MASKED,