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Diffstat (limited to 'src/intel/compiler/brw_eu_emit.c')
-rw-r--r--src/intel/compiler/brw_eu_emit.c18
1 files changed, 14 insertions, 4 deletions
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 0d5c755f9e8..08d64800f7a 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -3361,9 +3361,18 @@ brw_broadcast(struct brw_codegen *p,
* asserting would be mean.
*/
const unsigned i = idx.file == BRW_IMMEDIATE_VALUE ? idx.ud : 0;
- brw_MOV(p, dst,
- (align1 ? stride(suboffset(src, i), 0, 1, 0) :
- stride(suboffset(src, 4 * i), 0, 4, 1)));
+ src = align1 ? stride(suboffset(src, i), 0, 1, 0) :
+ stride(suboffset(src, 4 * i), 0, 4, 1);
+
+ if (type_sz(src.type) > 4 && !devinfo->has_64bit_float) {
+ brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 0),
+ subscript(src, BRW_REGISTER_TYPE_D, 0));
+ brw_set_default_swsb(p, tgl_swsb_null());
+ brw_MOV(p, subscript(dst, BRW_REGISTER_TYPE_D, 1),
+ subscript(src, BRW_REGISTER_TYPE_D, 1));
+ } else {
+ brw_MOV(p, dst, src);
+ }
} else {
/* From the Haswell PRM section "Register Region Restrictions":
*
@@ -3412,7 +3421,8 @@ brw_broadcast(struct brw_codegen *p,
/* Use indirect addressing to fetch the specified component. */
if (type_sz(src.type) > 4 &&
- (devinfo->is_cherryview || gen_device_info_is_9lp(devinfo))) {
+ (devinfo->is_cherryview || gen_device_info_is_9lp(devinfo) ||
+ !devinfo->has_64bit_float)) {
/* From the Cherryview PRM Vol 7. "Register Region Restrictions":
*
* "When source or destination datatype is 64b or operation is