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-rw-r--r--src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c
index a55adf15d8d..7ebfa408768 100644
--- a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c
+++ b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c
@@ -2586,8 +2586,6 @@ emit_intrinsic(struct ntv_context *ctx, nir_intrinsic_instr *intr)
break;
case nir_intrinsic_load_sample_mask_in:
- if (ctx->info->fs.post_depth_coverage)
- spirv_builder_emit_cap(&ctx->builder, SpvCapabilitySampleMaskPostDepthCoverage);
emit_load_uint_input(ctx, intr, &ctx->sample_mask_in_var, "gl_SampleMaskIn", SpvBuiltInSampleMask);
break;
@@ -3581,6 +3579,12 @@ nir_to_spirv(struct nir_shader *s, const struct zink_so_info *so_info, bool spir
spirv_builder_emit_cap(&ctx.builder, SpvCapabilitySampledBuffer);
switch (s->info.stage) {
+ case MESA_SHADER_FRAGMENT:
+ if (s->info.fs.post_depth_coverage &&
+ BITSET_TEST(s->info.system_values_read, SYSTEM_VALUE_SAMPLE_MASK_IN))
+ spirv_builder_emit_cap(&ctx.builder, SpvCapabilitySampleMaskPostDepthCoverage);
+ break;
+
case MESA_SHADER_TESS_CTRL:
case MESA_SHADER_TESS_EVAL:
spirv_builder_emit_cap(&ctx.builder, SpvCapabilityTessellation);