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-rw-r--r--src/gallium/winsys/amdgpu/drm/amdgpu_cs.c187
-rw-r--r--src/gallium/winsys/amdgpu/drm/amdgpu_cs.h13
-rw-r--r--src/gallium/winsys/d3d12/wgl/d3d12_wgl_framebuffer.cpp4
-rw-r--r--src/gallium/winsys/d3d12/wgl/d3d12_wgl_public.h2
-rw-r--r--src/gallium/winsys/freedreno/drm/freedreno_drm_public.h3
-rw-r--r--src/gallium/winsys/freedreno/drm/freedreno_drm_winsys.c5
-rw-r--r--src/gallium/winsys/kmsro/drm/kmsro_drm_winsys.c2
-rw-r--r--src/gallium/winsys/lima/drm/lima_drm_winsys.c8
-rw-r--r--src/gallium/winsys/radeon/drm/radeon_drm_winsys.c4
-rw-r--r--src/gallium/winsys/svga/drm/vmw_buffer.c34
-rw-r--r--src/gallium/winsys/virgl/common/virgl_resource_cache.c32
-rw-r--r--src/gallium/winsys/virgl/common/virgl_resource_cache.h31
-rw-r--r--src/gallium/winsys/virgl/drm/virgl_drm_winsys.c44
-rw-r--r--src/gallium/winsys/virgl/vtest/virgl_vtest_winsys.c27
14 files changed, 170 insertions, 226 deletions
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 543a191fc2e..6452d2ba4a8 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -761,24 +761,6 @@ static bool amdgpu_ib_new_buffer(struct amdgpu_winsys *ws,
return true;
}
-static unsigned amdgpu_ib_max_submit_dwords(enum ib_type ib_type)
-{
- /* The maximum IB size including all chained IBs. */
- switch (ib_type) {
- case IB_MAIN:
- /* Smaller submits means the GPU gets busy sooner and there is less
- * waiting for buffers and fences. Proof:
- * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
- */
- return 20 * 1024;
- case IB_PARALLEL_COMPUTE:
- /* Always chain this IB. */
- return UINT_MAX;
- default:
- unreachable("bad ib_type");
- }
-}
-
static bool amdgpu_get_new_ib(struct amdgpu_winsys *ws,
struct radeon_cmdbuf *rcs,
struct amdgpu_ib *ib,
@@ -800,7 +782,7 @@ static bool amdgpu_get_new_ib(struct amdgpu_winsys *ws,
if (!cs->has_chaining) {
ib_size = MAX2(ib_size,
4 * MIN2(util_next_power_of_two(ib->max_ib_size),
- amdgpu_ib_max_submit_dwords(ib->ib_type)));
+ IB_MAX_SUBMIT_DWORDS));
}
ib->max_ib_size = ib->max_ib_size - ib->max_ib_size / 32;
@@ -829,6 +811,9 @@ static bool amdgpu_get_new_ib(struct amdgpu_winsys *ws,
rcs->current.buf = (uint32_t*)(ib->ib_mapped + ib->used_ib_space);
+ if (ib->ib_type == IB_MAIN)
+ cs->csc->ib_main_addr = rcs->current.buf;
+
ib_size = ib->big_ib_buffer->size - ib->used_ib_space;
rcs->current.max_dw = ib_size / 4 - amdgpu_cs_epilog_dws(cs);
rcs->gpu_address = info->va_start;
@@ -908,9 +893,6 @@ static bool amdgpu_init_cs_context(struct amdgpu_winsys *ws,
assert(0);
}
- cs->ib[IB_PARALLEL_COMPUTE].ip_type = AMDGPU_HW_IP_COMPUTE;
- cs->ib[IB_PARALLEL_COMPUTE].flags = AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE;
-
cs->last_added_bo = NULL;
return true;
}
@@ -938,8 +920,6 @@ static void amdgpu_cs_context_cleanup(struct amdgpu_winsys *ws, struct amdgpu_cs
cleanup_fence_list(&cs->fence_dependencies);
cleanup_fence_list(&cs->syncobj_dependencies);
cleanup_fence_list(&cs->syncobj_to_signal);
- cleanup_fence_list(&cs->compute_fence_dependencies);
- cleanup_fence_list(&cs->compute_start_fence_dependencies);
cs->num_real_buffers = 0;
cs->num_slab_buffers = 0;
@@ -957,8 +937,6 @@ static void amdgpu_destroy_cs_context(struct amdgpu_winsys *ws, struct amdgpu_cs
FREE(cs->fence_dependencies.list);
FREE(cs->syncobj_dependencies.list);
FREE(cs->syncobj_to_signal.list);
- FREE(cs->compute_fence_dependencies.list);
- FREE(cs->compute_start_fence_dependencies.list);
}
@@ -997,7 +975,6 @@ amdgpu_cs_create(struct radeon_cmdbuf *rcs,
amdgpu_cs_chunk_fence_info_to_data(&fence_info, (void*)&cs->fence_chunk);
cs->main.ib_type = IB_MAIN;
- cs->compute_ib.ib_type = IB_PARALLEL_COMPUTE;
if (!amdgpu_init_cs_context(ctx->ws, &cs->csc1, ring_type)) {
FREE(cs);
@@ -1036,37 +1013,6 @@ amdgpu_cs_create(struct radeon_cmdbuf *rcs,
}
static bool
-amdgpu_cs_add_parallel_compute_ib(struct radeon_cmdbuf *compute_cs,
- struct radeon_cmdbuf *gfx_cs,
- bool uses_gds_ordered_append)
-{
- struct amdgpu_cs *cs = amdgpu_cs(gfx_cs);
- struct amdgpu_winsys *ws = cs->ws;
-
- if (cs->ring_type != RING_GFX)
- return false;
-
- /* only one secondary IB can be added */
- if (cs->compute_ib.ib_mapped)
- return false;
-
- /* Allocate the compute IB. */
- if (!amdgpu_get_new_ib(ws, compute_cs, &cs->compute_ib, cs))
- return false;
-
- if (uses_gds_ordered_append) {
- cs->csc1.ib[IB_PARALLEL_COMPUTE].flags |=
- AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID;
- cs->csc2.ib[IB_PARALLEL_COMPUTE].flags |=
- AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID;
- }
-
- cs->compute_ib.rcs = compute_cs;
- compute_cs->priv = cs;
- return true;
-}
-
-static bool
amdgpu_cs_setup_preemption(struct radeon_cmdbuf *rcs, const uint32_t *preamble_ib,
unsigned preamble_num_dw)
{
@@ -1128,12 +1074,9 @@ static bool amdgpu_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw,
bool force_chaining)
{
struct amdgpu_cs *cs = amdgpu_cs(rcs);
- struct amdgpu_ib *ib = rcs == cs->main.rcs ? &cs->main : &cs->compute_ib;
- unsigned requested_size = rcs->prev_dw + rcs->current.cdw + dw;
+ struct amdgpu_ib *ib = &cs->main;
unsigned cs_epilog_dw = amdgpu_cs_epilog_dws(cs);
unsigned need_byte_size = (dw + cs_epilog_dw) * 4;
- uint64_t va;
- uint32_t *new_ptr_ib_size;
assert(rcs->current.cdw <= rcs->current.max_dw);
@@ -1144,7 +1087,9 @@ static bool amdgpu_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw,
/* If force_chaining is true, we can't return. We have to chain. */
if (!force_chaining) {
- if (requested_size > amdgpu_ib_max_submit_dwords(ib->ib_type))
+ unsigned requested_size = rcs->prev_dw + rcs->current.cdw + dw;
+
+ if (requested_size > IB_MAX_SUBMIT_DWORDS)
return false;
ib->max_ib_size = MAX2(ib->max_ib_size, requested_size);
@@ -1177,7 +1122,7 @@ static bool amdgpu_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw,
return false;
assert(ib->used_ib_space == 0);
- va = amdgpu_winsys_bo(ib->big_ib_buffer)->va;
+ uint64_t va = amdgpu_winsys_bo(ib->big_ib_buffer)->va;
/* This space was originally reserved. */
rcs->current.max_dw += cs_epilog_dw;
@@ -1190,7 +1135,7 @@ static bool amdgpu_cs_check_space(struct radeon_cmdbuf *rcs, unsigned dw,
radeon_emit(rcs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
radeon_emit(rcs, va);
radeon_emit(rcs, va >> 32);
- new_ptr_ib_size = &rcs->current.buf[rcs->current.cdw++];
+ uint32_t *new_ptr_ib_size = &rcs->current.buf[rcs->current.cdw++];
assert((rcs->current.cdw & ib_pad_dw_mask) == 0);
assert((rcs->current.cdw & 7) == 0);
@@ -1287,18 +1232,6 @@ static void amdgpu_cs_add_fence_dependency(struct radeon_cmdbuf *rws,
util_queue_fence_wait(&fence->submitted);
- if (dependency_flags & RADEON_DEPENDENCY_PARALLEL_COMPUTE_ONLY) {
- /* Syncobjs are not needed here. */
- assert(!amdgpu_fence_is_syncobj(fence));
-
- if (acs->ws->info.has_scheduled_fence_dependency &&
- dependency_flags & RADEON_DEPENDENCY_START_FENCE)
- add_fence_to_list(&cs->compute_start_fence_dependencies, fence);
- else
- add_fence_to_list(&cs->compute_fence_dependencies, fence);
- return;
- }
-
/* Start fences are not needed here. */
assert(!(dependency_flags & RADEON_DEPENDENCY_START_FENCE));
@@ -1533,6 +1466,8 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index)
if (acs->ring_type == RING_GFX)
ws->gfx_bo_list_counter += cs->num_real_buffers;
+ bool noop = false;
+
if (acs->stop_exec_on_failure && acs->ctx->num_rejected_cs) {
r = -ECANCELED;
} else {
@@ -1590,66 +1525,6 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index)
num_chunks++;
}
- /* Submit the parallel compute IB first. */
- if (cs->ib[IB_PARALLEL_COMPUTE].ib_bytes > 0) {
- unsigned old_num_chunks = num_chunks;
-
- /* Add compute fence dependencies. */
- unsigned num_dependencies = cs->compute_fence_dependencies.num;
- if (num_dependencies) {
- struct drm_amdgpu_cs_chunk_dep *dep_chunk =
- alloca(num_dependencies * sizeof(*dep_chunk));
-
- for (unsigned i = 0; i < num_dependencies; i++) {
- struct amdgpu_fence *fence =
- (struct amdgpu_fence*)cs->compute_fence_dependencies.list[i];
-
- assert(util_queue_fence_is_signalled(&fence->submitted));
- amdgpu_cs_chunk_fence_to_dep(&fence->fence, &dep_chunk[i]);
- }
-
- chunks[num_chunks].chunk_id = AMDGPU_CHUNK_ID_DEPENDENCIES;
- chunks[num_chunks].length_dw = sizeof(dep_chunk[0]) / 4 * num_dependencies;
- chunks[num_chunks].chunk_data = (uintptr_t)dep_chunk;
- num_chunks++;
- }
-
- /* Add compute start fence dependencies. */
- unsigned num_start_dependencies = cs->compute_start_fence_dependencies.num;
- if (num_start_dependencies) {
- struct drm_amdgpu_cs_chunk_dep *dep_chunk =
- alloca(num_start_dependencies * sizeof(*dep_chunk));
-
- for (unsigned i = 0; i < num_start_dependencies; i++) {
- struct amdgpu_fence *fence =
- (struct amdgpu_fence*)cs->compute_start_fence_dependencies.list[i];
-
- assert(util_queue_fence_is_signalled(&fence->submitted));
- amdgpu_cs_chunk_fence_to_dep(&fence->fence, &dep_chunk[i]);
- }
-
- chunks[num_chunks].chunk_id = AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES;
- chunks[num_chunks].length_dw = sizeof(dep_chunk[0]) / 4 * num_start_dependencies;
- chunks[num_chunks].chunk_data = (uintptr_t)dep_chunk;
- num_chunks++;
- }
-
- /* Convert from dwords to bytes. */
- cs->ib[IB_PARALLEL_COMPUTE].ib_bytes *= 4;
- chunks[num_chunks].chunk_id = AMDGPU_CHUNK_ID_IB;
- chunks[num_chunks].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
- chunks[num_chunks].chunk_data = (uintptr_t)&cs->ib[IB_PARALLEL_COMPUTE];
- num_chunks++;
-
- r = acs->noop ? 0 : amdgpu_cs_submit_raw2(ws->dev, acs->ctx->ctx, bo_list,
- num_chunks, chunks, NULL);
- if (r)
- goto finalize;
-
- /* Back off the compute chunks. */
- num_chunks = old_num_chunks;
- }
-
/* Syncobj signals. */
unsigned num_syncobj_to_signal = cs->syncobj_to_signal.num;
if (num_syncobj_to_signal) {
@@ -1702,12 +1577,25 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index)
cs->ib[IB_MAIN].flags &= ~AMDGPU_IB_FLAGS_SECURE;
}
+ /* Apply RADEON_NOOP. */
+ if (acs->noop) {
+ if (acs->ring_type == RING_GFX) {
+ /* Reduce the IB size and fill it with NOP to make it like an empty IB. */
+ unsigned noop_size = MIN2(cs->ib[IB_MAIN].ib_bytes, ws->info.ib_alignment);
+
+ cs->ib_main_addr[0] = PKT3(PKT3_NOP, noop_size / 4 - 2, 0);
+ cs->ib[IB_MAIN].ib_bytes = noop_size;
+ } else {
+ noop = true;
+ }
+ }
+
assert(num_chunks <= ARRAY_SIZE(chunks));
- r = acs->noop ? 0 : amdgpu_cs_submit_raw2(ws->dev, acs->ctx->ctx, bo_list,
- num_chunks, chunks, &seq_no);
+ r = noop ? 0 : amdgpu_cs_submit_raw2(ws->dev, acs->ctx->ctx, bo_list,
+ num_chunks, chunks, &seq_no);
}
-finalize:
+
if (r) {
if (r == -ENOMEM)
fprintf(stderr, "amdgpu: Not enough memory for command submission.\n");
@@ -1719,7 +1607,7 @@ finalize:
acs->ctx->num_rejected_cs++;
ws->num_total_rejected_cs++;
- } else if (!acs->noop) {
+ } else if (!noop) {
/* Success. */
uint64_t *user_fence = NULL;
@@ -1741,7 +1629,7 @@ finalize:
cleanup:
/* If there was an error, signal the fence, because it won't be signalled
* by the hardware. */
- if (r || acs->noop)
+ if (r || noop)
amdgpu_fence_signalled(cs->fence);
cs->error_code = r;
@@ -1799,12 +1687,6 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs,
}
if (cs->ring_type == RING_GFX)
ws->gfx_ib_size_counter += (rcs->prev_dw + rcs->current.cdw) * 4;
-
- /* Also pad secondary IBs. */
- if (cs->compute_ib.ib_mapped) {
- while (cs->compute_ib.rcs->current.cdw & ib_pad_dw_mask)
- radeon_emit(cs->compute_ib.rcs, PKT3_NOP_PAD);
- }
break;
case RING_UVD:
case RING_UVD_ENC:
@@ -1840,9 +1722,6 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs,
/* Set IB sizes. */
amdgpu_ib_finalize(ws, rcs, &cs->main);
- if (cs->compute_ib.ib_mapped)
- amdgpu_ib_finalize(ws, cs->compute_ib.rcs, &cs->compute_ib);
-
/* Create a fence. */
amdgpu_fence_reference(&cur->fence, NULL);
if (cs->next_fence) {
@@ -1898,8 +1777,6 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs,
memset(cs->csc->buffer_indices_hashlist, -1, sizeof(cs->buffer_indices_hashlist));
amdgpu_get_new_ib(ws, rcs, &cs->main, cs);
- if (cs->compute_ib.ib_mapped)
- amdgpu_get_new_ib(ws, cs->compute_ib.rcs, &cs->compute_ib, cs);
if (cs->preamble_ib_bo) {
amdgpu_cs_add_buffer(rcs, cs->preamble_ib_bo, RADEON_USAGE_READ, 0,
@@ -1930,9 +1807,6 @@ static void amdgpu_cs_destroy(struct radeon_cmdbuf *rcs)
radeon_bo_reference(&cs->ws->dummy_ws.base, &cs->preamble_ib_bo, NULL);
radeon_bo_reference(&cs->ws->dummy_ws.base, &cs->main.big_ib_buffer, NULL);
FREE(rcs->prev);
- radeon_bo_reference(&cs->ws->dummy_ws.base, &cs->compute_ib.big_ib_buffer, NULL);
- if (cs->compute_ib.rcs)
- FREE(cs->compute_ib.rcs->prev);
amdgpu_destroy_cs_context(cs->ws, &cs->csc1);
amdgpu_destroy_cs_context(cs->ws, &cs->csc2);
amdgpu_fence_reference(&cs->next_fence, NULL);
@@ -1955,7 +1829,6 @@ void amdgpu_cs_init_functions(struct amdgpu_screen_winsys *ws)
ws->base.ctx_destroy = amdgpu_ctx_destroy;
ws->base.ctx_query_reset_status = amdgpu_ctx_query_reset_status;
ws->base.cs_create = amdgpu_cs_create;
- ws->base.cs_add_parallel_compute_ib = amdgpu_cs_add_parallel_compute_ib;
ws->base.cs_setup_preemption = amdgpu_cs_setup_preemption;
ws->base.cs_destroy = amdgpu_cs_destroy;
ws->base.cs_add_buffer = amdgpu_cs_add_buffer;
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
index 77bde4a070b..1ce8e5baec4 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
@@ -32,6 +32,12 @@
#include "util/u_memory.h"
#include "drm-uapi/amdgpu_drm.h"
+/* Smaller submits means the GPU gets busy sooner and there is less
+ * waiting for buffers and fences. Proof:
+ * http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
+ */
+#define IB_MAX_SUBMIT_DWORDS (20 * 1024)
+
struct amdgpu_ctx {
struct amdgpu_winsys *ws;
amdgpu_context_handle ctx;
@@ -58,7 +64,6 @@ struct amdgpu_cs_buffer {
enum ib_type {
IB_PREAMBLE,
IB_MAIN,
- IB_PARALLEL_COMPUTE,
IB_NUM,
};
@@ -90,6 +95,7 @@ struct amdgpu_fence_list {
struct amdgpu_cs_context {
struct drm_amdgpu_cs_chunk_ib ib[IB_NUM];
+ uint32_t *ib_main_addr; /* the beginning of IB before chaining */
/* Buffers. */
unsigned max_real_buffers;
@@ -115,10 +121,6 @@ struct amdgpu_cs_context {
struct amdgpu_fence_list syncobj_dependencies;
struct amdgpu_fence_list syncobj_to_signal;
- /* The compute IB uses the dependencies above + these: */
- struct amdgpu_fence_list compute_fence_dependencies;
- struct amdgpu_fence_list compute_start_fence_dependencies;
-
struct pipe_fence_handle *fence;
/* the error returned from cs_flush for non-async submissions */
@@ -132,7 +134,6 @@ struct amdgpu_cs_context {
struct amdgpu_cs {
struct amdgpu_ib main; /* must be first because this is inherited */
- struct amdgpu_ib compute_ib; /* optional parallel compute IB */
struct amdgpu_winsys *ws;
struct amdgpu_ctx *ctx;
enum ring_type ring_type;
diff --git a/src/gallium/winsys/d3d12/wgl/d3d12_wgl_framebuffer.cpp b/src/gallium/winsys/d3d12/wgl/d3d12_wgl_framebuffer.cpp
index b96dc52517f..e9a343b90e2 100644
--- a/src/gallium/winsys/d3d12/wgl/d3d12_wgl_framebuffer.cpp
+++ b/src/gallium/winsys/d3d12/wgl/d3d12_wgl_framebuffer.cpp
@@ -214,7 +214,7 @@ d3d12_wgl_framebuffer_get_resource(struct stw_winsys_framebuffer *pframebuffer,
struct stw_winsys_framebuffer *
d3d12_wgl_create_framebuffer(struct pipe_screen *screen,
- HDC hDC,
+ HWND hWnd,
int iPixelFormat)
{
const struct stw_pixelformat_info *pfi =
@@ -229,7 +229,7 @@ d3d12_wgl_create_framebuffer(struct pipe_screen *screen,
new (fb) struct d3d12_wgl_framebuffer();
- fb->window = WindowFromDC(hDC);
+ fb->window = hWnd;
fb->screen = d3d12_screen(screen);
fb->base.destroy = d3d12_wgl_framebuffer_destroy;
fb->base.resize = d3d12_wgl_framebuffer_resize;
diff --git a/src/gallium/winsys/d3d12/wgl/d3d12_wgl_public.h b/src/gallium/winsys/d3d12/wgl/d3d12_wgl_public.h
index ac5f2c75476..a690ade7471 100644
--- a/src/gallium/winsys/d3d12/wgl/d3d12_wgl_public.h
+++ b/src/gallium/winsys/d3d12/wgl/d3d12_wgl_public.h
@@ -50,7 +50,7 @@ d3d12_wgl_get_pfd_flags(struct pipe_screen *screen);
struct stw_winsys_framebuffer *
d3d12_wgl_create_framebuffer(struct pipe_screen *screen,
- HDC hDC,
+ HWND hWnd,
int iPixelFormat);
#ifdef __cplusplus
diff --git a/src/gallium/winsys/freedreno/drm/freedreno_drm_public.h b/src/gallium/winsys/freedreno/drm/freedreno_drm_public.h
index 2f5591e867a..a15f6cf8683 100644
--- a/src/gallium/winsys/freedreno/drm/freedreno_drm_public.h
+++ b/src/gallium/winsys/freedreno/drm/freedreno_drm_public.h
@@ -5,6 +5,7 @@
struct pipe_screen;
struct renderonly;
-struct pipe_screen *fd_drm_screen_create(int drmFD, struct renderonly *ro);
+struct pipe_screen *fd_drm_screen_create(int drmFD, struct renderonly *ro,
+ const struct pipe_screen_config *config);
#endif
diff --git a/src/gallium/winsys/freedreno/drm/freedreno_drm_winsys.c b/src/gallium/winsys/freedreno/drm/freedreno_drm_winsys.c
index 211e1656429..3e4109e3e9a 100644
--- a/src/gallium/winsys/freedreno/drm/freedreno_drm_winsys.c
+++ b/src/gallium/winsys/freedreno/drm/freedreno_drm_winsys.c
@@ -69,7 +69,8 @@ fd_drm_screen_destroy(struct pipe_screen *pscreen)
}
struct pipe_screen *
-fd_drm_screen_create(int fd, struct renderonly *ro)
+fd_drm_screen_create(int fd, struct renderonly *ro,
+ const struct pipe_screen_config *config)
{
struct pipe_screen *pscreen = NULL;
@@ -88,7 +89,7 @@ fd_drm_screen_create(int fd, struct renderonly *ro)
if (!dev)
goto unlock;
- pscreen = fd_screen_create(dev, ro);
+ pscreen = fd_screen_create(dev, ro, config);
if (pscreen) {
int fd = fd_device_fd(dev);
diff --git a/src/gallium/winsys/kmsro/drm/kmsro_drm_winsys.c b/src/gallium/winsys/kmsro/drm/kmsro_drm_winsys.c
index ec927986c80..6d2f0cabd67 100644
--- a/src/gallium/winsys/kmsro/drm/kmsro_drm_winsys.c
+++ b/src/gallium/winsys/kmsro/drm/kmsro_drm_winsys.c
@@ -91,7 +91,7 @@ struct pipe_screen *kmsro_drm_screen_create(int fd,
ro->gpu_fd = drmOpenWithType("msm", NULL, DRM_NODE_RENDER);
if (ro->gpu_fd >= 0) {
ro->create_for_resource = renderonly_create_kms_dumb_buffer_for_resource;
- screen = fd_drm_screen_create(ro->gpu_fd, ro);
+ screen = fd_drm_screen_create(ro->gpu_fd, ro, config);
if (!screen)
goto out_free;
diff --git a/src/gallium/winsys/lima/drm/lima_drm_winsys.c b/src/gallium/winsys/lima/drm/lima_drm_winsys.c
index b23f1113776..9c8cd933e79 100644
--- a/src/gallium/winsys/lima/drm/lima_drm_winsys.c
+++ b/src/gallium/winsys/lima/drm/lima_drm_winsys.c
@@ -47,8 +47,14 @@ lima_drm_screen_destroy(struct pipe_screen *pscreen)
mtx_lock(&lima_screen_mutex);
destroy = --screen->refcnt == 0;
- if (destroy)
+ if (destroy) {
_mesa_hash_table_remove_key(fd_tab, intptr_to_pointer(fd));
+
+ if (!fd_tab->entries) {
+ _mesa_hash_table_destroy(fd_tab, NULL);
+ fd_tab = NULL;
+ }
+ }
mtx_unlock(&lima_screen_mutex);
if (destroy) {
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index ef9ec590d5d..22d8b98ac0d 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -315,6 +315,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
/* Check for UVD and VCE */
ws->info.has_video_hw.uvd_decode = false;
+ ws->info.has_video_hw.vce_encode = false;
ws->info.vce_fw_version = 0x00000000;
if (ws->info.drm_minor >= 32) {
uint32_t value = RADEON_CS_RING_UVD;
@@ -332,6 +333,7 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
"VCE FW version", &value)) {
ws->info.vce_fw_version = value;
ws->info.num_rings[RING_VCE] = 1;
+ ws->info.has_video_hw.vce_encode = true;
}
}
}
@@ -605,8 +607,6 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
ws->info.max_wave64_per_simd = 10;
ws->info.num_physical_sgprs_per_simd = 512;
ws->info.num_physical_wave64_vgprs_per_simd = 256;
- /* Potential hang on Kabini: */
- ws->info.use_late_alloc = ws->info.family != CHIP_KABINI;
ws->info.has_3d_cube_border_color_mipmap = true;
ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL ||
diff --git a/src/gallium/winsys/svga/drm/vmw_buffer.c b/src/gallium/winsys/svga/drm/vmw_buffer.c
index d537c8be96e..6c235a9a486 100644
--- a/src/gallium/winsys/svga/drm/vmw_buffer.c
+++ b/src/gallium/winsys/svga/drm/vmw_buffer.c
@@ -357,32 +357,30 @@ vmw_svga_winsys_buffer_map(struct svga_winsys_screen *sws,
enum pipe_map_flags flags)
{
void *map;
+ enum pb_usage_flags pb_flags = 0;
(void)sws;
if (flags & PIPE_MAP_UNSYNCHRONIZED)
flags &= ~PIPE_MAP_DONTBLOCK;
- /* NOTE: we're passing PIPE_MAP_x flags instead of
- * PB_USAGE_x flags here. We should probably fix that.
- */
- STATIC_ASSERT((unsigned) PB_USAGE_CPU_READ ==
- (unsigned) PIPE_MAP_READ);
- STATIC_ASSERT((unsigned) PB_USAGE_CPU_WRITE ==
- (unsigned) PIPE_MAP_WRITE);
- STATIC_ASSERT((unsigned) PB_USAGE_GPU_READ ==
- (unsigned) PIPE_MAP_DIRECTLY);
- STATIC_ASSERT((unsigned) PB_USAGE_DONTBLOCK ==
- (unsigned) PIPE_MAP_DONTBLOCK);
- STATIC_ASSERT((unsigned) PB_USAGE_UNSYNCHRONIZED ==
- (unsigned) PIPE_MAP_UNSYNCHRONIZED);
- STATIC_ASSERT((unsigned) PB_USAGE_PERSISTENT ==
- (unsigned) PIPE_MAP_PERSISTENT);
-
- map = pb_map(vmw_pb_buffer(buf), flags & PB_USAGE_ALL, NULL);
+ if (flags & PIPE_MAP_READ)
+ pb_flags |= PB_USAGE_CPU_READ;
+ if (flags & PIPE_MAP_WRITE)
+ pb_flags |= PB_USAGE_CPU_WRITE;
+ if (flags & PIPE_MAP_DIRECTLY)
+ pb_flags |= PB_USAGE_GPU_READ;
+ if (flags & PIPE_MAP_DONTBLOCK)
+ pb_flags |= PB_USAGE_DONTBLOCK;
+ if (flags & PIPE_MAP_UNSYNCHRONIZED)
+ pb_flags |= PB_USAGE_UNSYNCHRONIZED;
+ if (flags & PIPE_MAP_PERSISTENT)
+ pb_flags |= PB_USAGE_PERSISTENT;
+
+ map = pb_map(vmw_pb_buffer(buf), pb_flags, NULL);
#ifdef DEBUG
if (map != NULL)
- debug_flush_map(buf->fbuf, flags);
+ debug_flush_map(buf->fbuf, pb_flags);
#endif
return map;
diff --git a/src/gallium/winsys/virgl/common/virgl_resource_cache.c b/src/gallium/winsys/virgl/common/virgl_resource_cache.c
index d7d6a610ea9..ba00a055f10 100644
--- a/src/gallium/winsys/virgl/common/virgl_resource_cache.c
+++ b/src/gallium/winsys/virgl/common/virgl_resource_cache.c
@@ -28,18 +28,22 @@
* data of the specified size, bind and format.
*/
static bool
-virgl_resource_cache_entry_is_compatible(struct virgl_resource_cache_entry *entry,
- uint32_t size, uint32_t bind,
- uint32_t format, uint32_t flags)
+virgl_resource_cache_entry_is_compatible(struct virgl_resource_cache_entry *entry, struct virgl_resource_params params)
{
- return (entry->bind == bind &&
- entry->format == format &&
- entry->size >= size &&
- entry->flags == flags &&
- /* We don't want to waste space, so don't reuse resource storage to
- * hold much smaller (< 50%) sizes.
- */
- entry->size <= size * 2);
+ if (entry->params.target == PIPE_BUFFER) {
+ return (entry->params.bind == params.bind &&
+ entry->params.format == params.format &&
+ entry->params.size >= params.size &&
+ entry->params.flags == params.flags &&
+ /* We don't want to waste space, so don't reuse resource storage to
+ * hold much smaller (< 50%) sizes.
+ */
+ entry->params.size <= params.size * 2 &&
+ entry->params.width >= params.width &&
+ entry->params.target == params.target);
+ } else {
+ return memcmp(&entry->params, &params, sizeof(params)) == 0;
+ }
}
static void
@@ -97,8 +101,7 @@ virgl_resource_cache_add(struct virgl_resource_cache *cache,
struct virgl_resource_cache_entry *
virgl_resource_cache_remove_compatible(struct virgl_resource_cache *cache,
- uint32_t size, uint32_t bind,
- uint32_t format, uint32_t flags)
+ struct virgl_resource_params params)
{
const int64_t now = os_time_get();
struct virgl_resource_cache_entry *compat_entry = NULL;
@@ -110,8 +113,7 @@ virgl_resource_cache_remove_compatible(struct virgl_resource_cache *cache,
list_for_each_entry_safe(struct virgl_resource_cache_entry,
entry, &cache->resources, head) {
const bool compatible =
- virgl_resource_cache_entry_is_compatible(entry, size, bind, format,
- flags);
+ virgl_resource_cache_entry_is_compatible(entry, params);
if (compatible) {
if (!cache->entry_is_busy_func(entry, cache->user_data))
diff --git a/src/gallium/winsys/virgl/common/virgl_resource_cache.h b/src/gallium/winsys/virgl/common/virgl_resource_cache.h
index e5f710dc2cc..e7979c4db2c 100644
--- a/src/gallium/winsys/virgl/common/virgl_resource_cache.h
+++ b/src/gallium/winsys/virgl/common/virgl_resource_cache.h
@@ -27,15 +27,27 @@
#include <stdint.h>
#include "util/list.h"
+#include "gallium/include/pipe/p_defines.h"
-struct virgl_resource_cache_entry {
- struct list_head head;
- int64_t timeout_start;
- int64_t timeout_end;
+struct virgl_resource_params {
uint32_t size;
uint32_t bind;
uint32_t format;
uint32_t flags;
+ uint32_t nr_samples;
+ uint32_t width;
+ uint32_t height;
+ uint32_t depth;
+ uint32_t array_size;
+ uint32_t last_level;
+ enum pipe_texture_target target;
+};
+
+struct virgl_resource_cache_entry {
+ struct list_head head;
+ int64_t timeout_start;
+ int64_t timeout_end;
+ struct virgl_resource_params params;
};
/* Pointer to a function that returns whether the resource represented by
@@ -81,8 +93,7 @@ virgl_resource_cache_add(struct virgl_resource_cache *cache,
*/
struct virgl_resource_cache_entry *
virgl_resource_cache_remove_compatible(struct virgl_resource_cache *cache,
- uint32_t size, uint32_t bind,
- uint32_t format, uint32_t flags);
+ struct virgl_resource_params params);
/** Empties the resource cache. */
void
@@ -90,13 +101,9 @@ virgl_resource_cache_flush(struct virgl_resource_cache *cache);
static inline void
virgl_resource_cache_entry_init(struct virgl_resource_cache_entry *entry,
- uint32_t size, uint32_t bind,
- uint32_t format, uint32_t flags)
+ struct virgl_resource_params params)
{
- entry->size = size;
- entry->bind = bind;
- entry->format = format;
- entry->flags = flags;
+ entry->params = params;
}
#endif
diff --git a/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c b/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
index dfa145a73f7..752632c030c 100644
--- a/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
+++ b/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
@@ -63,6 +63,9 @@ static inline boolean can_cache_resource(uint32_t bind)
bind == VIRGL_BIND_VERTEX_BUFFER ||
bind == VIRGL_BIND_CUSTOM ||
bind == VIRGL_BIND_STAGING ||
+ bind == VIRGL_BIND_DEPTH_STENCIL ||
+ bind == VIRGL_BIND_SAMPLER_VIEW ||
+ bind == VIRGL_BIND_RENDER_TARGET ||
bind == 0;
}
@@ -176,6 +179,17 @@ virgl_drm_winsys_resource_create_blob(struct virgl_winsys *qws,
struct virgl_drm_winsys *qdws = virgl_drm_winsys(qws);
struct drm_virtgpu_resource_create_blob drm_rc_blob = { 0 };
struct virgl_hw_res *res;
+ struct virgl_resource_params params = { .size = size,
+ .bind = bind,
+ .format = format,
+ .flags = flags,
+ .nr_samples = nr_samples,
+ .width = width,
+ .height = height,
+ .depth = depth,
+ .array_size = array_size,
+ .last_level = last_level,
+ .target = target };
res = CALLOC_STRUCT(virgl_hw_res);
if (!res)
@@ -224,8 +238,7 @@ virgl_drm_winsys_resource_create_blob(struct virgl_winsys *qws,
pipe_reference_init(&res->reference, 1);
p_atomic_set(&res->external, false);
p_atomic_set(&res->num_cs_references, 0);
- virgl_resource_cache_entry_init(&res->cache_entry, size, bind, format,
- flags);
+ virgl_resource_cache_entry_init(&res->cache_entry, params);
return res;
}
@@ -248,6 +261,17 @@ virgl_drm_winsys_resource_create(struct virgl_winsys *qws,
int ret;
struct virgl_hw_res *res;
uint32_t stride = width * util_format_get_blocksize(format);
+ struct virgl_resource_params params = { .size = size,
+ .bind = bind,
+ .format = format,
+ .flags = 0,
+ .nr_samples = nr_samples,
+ .width = width,
+ .height = height,
+ .depth = depth,
+ .array_size = array_size,
+ .last_level = last_level,
+ .target = target };
res = CALLOC_STRUCT(virgl_hw_res);
if (!res)
@@ -289,7 +313,7 @@ virgl_drm_winsys_resource_create(struct virgl_winsys *qws,
*/
p_atomic_set(&res->maybe_busy, for_fencing);
- virgl_resource_cache_entry_init(&res->cache_entry, size, bind, format, 0);
+ virgl_resource_cache_entry_init(&res->cache_entry, params);
return res;
}
@@ -390,14 +414,24 @@ virgl_drm_winsys_resource_cache_create(struct virgl_winsys *qws,
struct virgl_drm_winsys *qdws = virgl_drm_winsys(qws);
struct virgl_hw_res *res;
struct virgl_resource_cache_entry *entry;
+ struct virgl_resource_params params = { .size = size,
+ .bind = bind,
+ .format = format,
+ .flags = flags,
+ .nr_samples = nr_samples,
+ .width = width,
+ .height = height,
+ .depth = depth,
+ .array_size = array_size,
+ .last_level = last_level,
+ .target = target };
if (!can_cache_resource(bind))
goto alloc;
mtx_lock(&qdws->mutex);
- entry = virgl_resource_cache_remove_compatible(&qdws->cache, size,
- bind, format, flags);
+ entry = virgl_resource_cache_remove_compatible(&qdws->cache, params);
if (entry) {
res = cache_entry_container_res(entry);
mtx_unlock(&qdws->mutex);
diff --git a/src/gallium/winsys/virgl/vtest/virgl_vtest_winsys.c b/src/gallium/winsys/virgl/vtest/virgl_vtest_winsys.c
index 669cd763e56..5c7d73ab097 100644
--- a/src/gallium/winsys/virgl/vtest/virgl_vtest_winsys.c
+++ b/src/gallium/winsys/virgl/vtest/virgl_vtest_winsys.c
@@ -238,6 +238,17 @@ virgl_vtest_winsys_resource_create(struct virgl_winsys *vws,
struct virgl_hw_res *res;
static int handle = 1;
int fd = -1;
+ struct virgl_resource_params params = { .size = size,
+ .bind = bind,
+ .format = format,
+ .flags = 0,
+ .nr_samples = nr_samples,
+ .width = width,
+ .height = height,
+ .depth = depth,
+ .array_size = array_size,
+ .last_level = last_level,
+ .target = target };
res = CALLOC_STRUCT(virgl_hw_res);
if (!res)
@@ -291,7 +302,7 @@ virgl_vtest_winsys_resource_create(struct virgl_winsys *vws,
}
out:
- virgl_resource_cache_entry_init(&res->cache_entry, size, bind, format, 0);
+ virgl_resource_cache_entry_init(&res->cache_entry, params);
res->res_handle = handle++;
pipe_reference_init(&res->reference, 1);
p_atomic_set(&res->num_cs_references, 0);
@@ -353,14 +364,24 @@ virgl_vtest_winsys_resource_cache_create(struct virgl_winsys *vws,
struct virgl_vtest_winsys *vtws = virgl_vtest_winsys(vws);
struct virgl_hw_res *res;
struct virgl_resource_cache_entry *entry;
+ struct virgl_resource_params params = { .size = size,
+ .bind = bind,
+ .format = format,
+ .flags = 0,
+ .nr_samples = nr_samples,
+ .width = width,
+ .height = height,
+ .depth = depth,
+ .array_size = array_size,
+ .last_level = last_level,
+ .target = target };
if (!can_cache_resource_with_bind(bind))
goto alloc;
mtx_lock(&vtws->mutex);
- entry = virgl_resource_cache_remove_compatible(&vtws->cache, size,
- bind, format, 0);
+ entry = virgl_resource_cache_remove_compatible(&vtws->cache, params);
if (entry) {
res = cache_entry_container_res(entry);
mtx_unlock(&vtws->mutex);