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-rw-r--r--src/gallium/drivers/radeonsi/si_descriptors.c2
-rw-r--r--src/gallium/drivers/radeonsi/si_state.c6
-rw-r--r--src/gallium/drivers/radeonsi/si_texture.c8
3 files changed, 8 insertions, 8 deletions
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index ba7bd9e6ea3..0e4dc81de40 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -314,7 +314,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture
else
va += tex->surface.u.gfx9.surf_offset;
} else {
- va += base_level_info->offset;
+ va += (uint64_t)base_level_info->offset_256B * 256;
}
state[0] = va >> 8;
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index c09e0ed6fb1..1113e4ad54a 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2506,9 +2506,9 @@ static void si_init_depth_surface(struct si_context *sctx, struct si_surface *su
assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
surf->db_depth_base =
- (tex->buffer.gpu_address + tex->surface.u.legacy.level[level].offset) >> 8;
+ (tex->buffer.gpu_address >> 8) + tex->surface.u.legacy.level[level].offset_256B;
surf->db_stencil_base =
- (tex->buffer.gpu_address + tex->surface.u.legacy.stencil_level[level].offset) >> 8;
+ (tex->buffer.gpu_address >> 8) + tex->surface.u.legacy.stencil_level[level].offset_256B;
z_info =
S_028040_FORMAT(format) | S_028040_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples));
@@ -3127,7 +3127,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
- cb_color_base += level_info->offset >> 8;
+ cb_color_base += level_info->offset_256B;
/* Only macrotiled modes can set tile swizzle. */
if (level_info->mode == RADEON_SURF_MODE_2D)
cb_color_base |= tex->surface.tile_swizzle;
diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index 30f2cea12e4..ce750fe3d90 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -142,11 +142,11 @@ static unsigned si_texture_get_offset(struct si_screen *sscreen, struct si_textu
*layer_stride = (uint64_t)tex->surface.u.legacy.level[level].slice_size_dw * 4;
if (!box)
- return tex->surface.u.legacy.level[level].offset;
+ return (uint64_t)tex->surface.u.legacy.level[level].offset_256B * 256;
/* Each texture is an array of mipmap levels. Each level is
* an array of slices. */
- return tex->surface.u.legacy.level[level].offset +
+ return (uint64_t)tex->surface.u.legacy.level[level].offset_256B * 256 +
box->z * (uint64_t)tex->surface.u.legacy.level[level].slice_size_dw * 4 +
(box->y / tex->surface.blk_h * tex->surface.u.legacy.level[level].nblk_x +
box->x / tex->surface.blk_w) *
@@ -846,7 +846,7 @@ void si_print_texture_info(struct si_screen *sscreen, struct si_texture *tex,
" Level[%i]: offset=%" PRIu64 ", slice_size=%" PRIu64 ", "
"npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
"mode=%u, tiling_index = %u\n",
- i, tex->surface.u.legacy.level[i].offset,
+ i, (uint64_t)tex->surface.u.legacy.level[i].offset_256B * 256,
(uint64_t)tex->surface.u.legacy.level[i].slice_size_dw * 4,
u_minify(tex->buffer.b.b.width0, i), u_minify(tex->buffer.b.b.height0, i),
u_minify(tex->buffer.b.b.depth0, i), tex->surface.u.legacy.level[i].nblk_x,
@@ -860,7 +860,7 @@ void si_print_texture_info(struct si_screen *sscreen, struct si_texture *tex,
"slice_size=%" PRIu64 ", npix_x=%u, "
"npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
"mode=%u, tiling_index = %u\n",
- i, tex->surface.u.legacy.stencil_level[i].offset,
+ i, (uint64_t)tex->surface.u.legacy.stencil_level[i].offset_256B * 256,
(uint64_t)tex->surface.u.legacy.stencil_level[i].slice_size_dw * 4,
u_minify(tex->buffer.b.b.width0, i), u_minify(tex->buffer.b.b.height0, i),
u_minify(tex->buffer.b.b.depth0, i),