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-rw-r--r--src/gallium/drivers/r600/evergreen_state.c24
-rw-r--r--src/gallium/drivers/r600/r600_state.c22
-rw-r--r--src/gallium/drivers/r600/r600_texture.c12
-rw-r--r--src/gallium/drivers/r600/radeon_uvd.c2
-rw-r--r--src/gallium/drivers/r600/radeon_video.c2
5 files changed, 31 insertions, 31 deletions
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index dce4b5c33f0..f9340baa6e8 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -847,7 +847,7 @@ static int evergreen_fill_tex_resource_words(struct r600_context *rctx,
tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
S_030004_TEX_DEPTH(depth - 1) |
S_030004_ARRAY_MODE(array_mode));
- tex_resource_words[2] = (surflevel[base_level].offset + va) >> 8;
+ tex_resource_words[2] = ((uint64_t)surflevel[base_level].offset_256B * 256 + va) >> 8;
*skip_mip_address_reloc = false;
/* TEX_RESOURCE_WORD3.MIP_ADDRESS */
@@ -861,9 +861,9 @@ static int evergreen_fill_tex_resource_words(struct r600_context *rctx,
tex_resource_words[3] = (tmp->fmask.offset + va) >> 8;
}
} else if (last_level && texture->nr_samples <= 1) {
- tex_resource_words[3] = (surflevel[1].offset + va) >> 8;
+ tex_resource_words[3] = ((uint64_t)surflevel[1].offset_256B * 256 + va) >> 8;
} else {
- tex_resource_words[3] = (surflevel[base_level].offset + va) >> 8;
+ tex_resource_words[3] = ((uint64_t)surflevel[base_level].offset_256B * 256 + va) >> 8;
}
last_layer = params->last_layer;
@@ -1124,7 +1124,7 @@ static void evergreen_set_color_surface_common(struct r600_context *rctx,
bool blend_clamp = 0, blend_bypass = 0, do_endian_swap = FALSE;
int i;
- color->offset = rtex->surface.u.legacy.level[level].offset;
+ color->offset = (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256;
color->view = S_028C6C_SLICE_START(first_layer) |
S_028C6C_SLICE_MAX(last_layer);
@@ -1361,7 +1361,7 @@ static void evergreen_init_depth_surface(struct r600_context *rctx,
assert(format != ~0);
offset = rtex->resource.gpu_address;
- offset += rtex->surface.u.legacy.level[level].offset;
+ offset += (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256;
switch (rtex->surface.u.legacy.level[level].mode) {
case RADEON_SURF_MODE_2D:
@@ -1411,7 +1411,7 @@ static void evergreen_init_depth_surface(struct r600_context *rctx,
stile_split = eg_tile_split(stile_split);
- stencil_offset = rtex->surface.u.legacy.stencil_level[level].offset;
+ stencil_offset = (uint64_t)rtex->surface.u.legacy.stencil_level[level].offset_256B * 256;
stencil_offset += rtex->resource.gpu_address;
surf->db_stencil_base = stencil_offset >> 8;
@@ -3813,8 +3813,8 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx,
x = src_x;
y = src_y;
z = src_z;
- base = rsrc->surface.u.legacy.level[src_level].offset;
- addr = rdst->surface.u.legacy.level[dst_level].offset;
+ base = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256;
+ addr = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256;
addr += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
addr += dst_y * pitch + dst_x * bpp;
bank_h = eg_bank_wh(rsrc->surface.u.legacy.bankh);
@@ -3838,8 +3838,8 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx,
x = dst_x;
y = dst_y;
z = dst_z;
- base = rdst->surface.u.legacy.level[dst_level].offset;
- addr = rsrc->surface.u.legacy.level[src_level].offset;
+ base = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256;
+ addr = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256;
addr += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_z;
addr += src_y * pitch + src_x * bpp;
bank_h = eg_bank_wh(rdst->surface.u.legacy.bankh);
@@ -3961,10 +3961,10 @@ static void evergreen_dma_copy(struct pipe_context *ctx,
* dst_x/y == 0
* dst_pitch == src_pitch
*/
- src_offset= rsrc->surface.u.legacy.level[src_level].offset;
+ src_offset= (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256;
src_offset += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_box->z;
src_offset += src_y * src_pitch + src_x * bpp;
- dst_offset = rdst->surface.u.legacy.level[dst_level].offset;
+ dst_offset = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256;
dst_offset += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
dst_offset += dst_y * dst_pitch + dst_x * bpp;
evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset,
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 56796244cfd..6eb2bd42b1c 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -755,11 +755,11 @@ r600_create_sampler_view_custom(struct pipe_context *ctx,
view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
S_038004_TEX_DEPTH(depth - 1) |
S_038004_DATA_FORMAT(format));
- view->tex_resource_words[2] = tmp->surface.u.legacy.level[offset_level].offset >> 8;
+ view->tex_resource_words[2] = tmp->surface.u.legacy.level[offset_level].offset_256B;
if (offset_level >= tmp->resource.b.b.last_level) {
- view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level].offset >> 8;
+ view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level].offset_256B;
} else {
- view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level + 1].offset >> 8;
+ view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level + 1].offset_256B;
}
view->tex_resource_words[4] = (word4 |
S_038010_REQUEST_SIZE(1) |
@@ -824,7 +824,7 @@ static void r600_init_color_surface(struct r600_context *rctx,
assert(rtex);
}
- offset = rtex->surface.u.legacy.level[level].offset;
+ offset = (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256;
color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
@@ -1041,7 +1041,7 @@ static void r600_init_depth_surface(struct r600_context *rctx,
unsigned level, pitch, slice, format, offset, array_mode;
level = surf->base.u.tex.level;
- offset = rtex->surface.u.legacy.level[level].offset;
+ offset = (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256;
pitch = rtex->surface.u.legacy.level[level].nblk_x / 8 - 1;
slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64;
if (slice) {
@@ -2884,8 +2884,8 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx,
x = src_x;
y = src_y;
z = src_z;
- base = rsrc->surface.u.legacy.level[src_level].offset;
- addr = rdst->surface.u.legacy.level[dst_level].offset;
+ base = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256;
+ addr = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256;
addr += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
addr += dst_y * pitch + dst_x * bpp;
} else {
@@ -2903,8 +2903,8 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx,
x = dst_x;
y = dst_y;
z = dst_z;
- base = rdst->surface.u.legacy.level[dst_level].offset;
- addr = rsrc->surface.u.legacy.level[src_level].offset;
+ base = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256;
+ addr = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256;
addr += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_z;
addr += src_y * pitch + src_x * bpp;
}
@@ -3007,10 +3007,10 @@ static void r600_dma_copy(struct pipe_context *ctx,
* dst_x/y == 0
* dst_pitch == src_pitch
*/
- src_offset= rsrc->surface.u.legacy.level[src_level].offset;
+ src_offset= (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256;
src_offset += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_box->z;
src_offset += src_y * src_pitch + src_x * bpp;
- dst_offset = rdst->surface.u.legacy.level[dst_level].offset;
+ dst_offset = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256;
dst_offset += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
dst_offset += dst_y * dst_pitch + dst_x * bpp;
size = src_box->height * src_pitch;
diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c
index afa44af5d2b..7f461ac051a 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -183,11 +183,11 @@ static unsigned r600_texture_get_offset(struct r600_common_screen *rscreen,
*layer_stride = (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4;
if (!box)
- return rtex->surface.u.legacy.level[level].offset;
+ return (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256;
/* Each texture is an array of mipmap levels. Each level is
* an array of slices. */
- return rtex->surface.u.legacy.level[level].offset +
+ return (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256 +
box->z * (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4 +
(box->y / rtex->surface.blk_h *
rtex->surface.u.legacy.level[level].nblk_x +
@@ -262,7 +262,7 @@ static int r600_init_surface(struct r600_common_screen *rscreen,
if (offset) {
for (i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
- surface->u.legacy.level[i].offset += offset;
+ surface->u.legacy.level[i].offset_256B += offset / 256;
}
return 0;
@@ -455,7 +455,7 @@ static void r600_texture_get_info(struct pipe_screen* screen,
return;
if (resource->target != PIPE_BUFFER) {
- offset = rtex->surface.u.legacy.level[0].offset;
+ offset = (uint64_t)rtex->surface.u.legacy.level[0].offset_256B * 256;
stride = rtex->surface.u.legacy.level[0].nblk_x *
rtex->surface.bpe;
}
@@ -868,7 +868,7 @@ void r600_print_texture_info(struct r600_common_screen *rscreen,
u_log_printf(log, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
"npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
"mode=%u, tiling_index = %u\n",
- i, rtex->surface.u.legacy.level[i].offset,
+ i, (uint64_t)rtex->surface.u.legacy.level[i].offset_256B * 256,
(uint64_t)rtex->surface.u.legacy.level[i].slice_size_dw * 4,
u_minify(rtex->resource.b.b.width0, i),
u_minify(rtex->resource.b.b.height0, i),
@@ -886,7 +886,7 @@ void r600_print_texture_info(struct r600_common_screen *rscreen,
"slice_size=%"PRIu64", npix_x=%u, "
"npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
"mode=%u, tiling_index = %u\n",
- i, rtex->surface.u.legacy.stencil_level[i].offset,
+ i, (uint64_t)rtex->surface.u.legacy.stencil_level[i].offset_256B * 256,
(uint64_t)rtex->surface.u.legacy.stencil_level[i].slice_size_dw * 4,
u_minify(rtex->resource.b.b.width0, i),
u_minify(rtex->resource.b.b.height0, i),
diff --git a/src/gallium/drivers/r600/radeon_uvd.c b/src/gallium/drivers/r600/radeon_uvd.c
index 4d0e0bf83c3..fa22ba586ae 100644
--- a/src/gallium/drivers/r600/radeon_uvd.c
+++ b/src/gallium/drivers/r600/radeon_uvd.c
@@ -1170,7 +1170,7 @@ error:
/* calculate top/bottom offset */
static unsigned texture_offset(struct radeon_surf *surface, unsigned layer)
{
- return surface->u.legacy.level[0].offset +
+ return (uint64_t)surface->u.legacy.level[0].offset_256B * 256 +
layer * (uint64_t)surface->u.legacy.level[0].slice_size_dw * 4;
}
diff --git a/src/gallium/drivers/r600/radeon_video.c b/src/gallium/drivers/r600/radeon_video.c
index a49c0a0120d..1ebb8708de4 100644
--- a/src/gallium/drivers/r600/radeon_video.c
+++ b/src/gallium/drivers/r600/radeon_video.c
@@ -180,7 +180,7 @@ void rvid_join_surfaces(struct r600_common_context *rctx,
surfaces[i]->u.legacy.tile_split = surfaces[best_tiling]->u.legacy.tile_split;
for (j = 0; j < ARRAY_SIZE(surfaces[i]->u.legacy.level); ++j)
- surfaces[i]->u.legacy.level[j].offset += off;
+ surfaces[i]->u.legacy.level[j].offset_256B += off / 256;
off += surfaces[i]->surf_size;
}