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Diffstat (limited to 'src/gallium/drivers/nouveau/nv50/nv50_screen.c')
-rw-r--r--src/gallium/drivers/nouveau/nv50/nv50_screen.c296
1 files changed, 74 insertions, 222 deletions
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
index b2a0b16eff4..dc1d36aa565 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -22,12 +22,13 @@
#include <errno.h>
#include <xf86drm.h>
-#include <nouveau_drm.h>
+#include "drm-uapi/nouveau_drm.h"
#include "util/format/u_format.h"
#include "util/format/u_format_s3tc.h"
#include "util/u_screen.h"
#include "pipe/p_screen.h"
-#include "compiler/nir/nir.h"
+
+#include "nv50_ir_driver.h"
#include "nv50/nv50_context.h"
#include "nv50/nv50_screen.h"
@@ -103,9 +104,9 @@ nv50_screen_is_format_supported(struct pipe_screen *pscreen,
static int
nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
{
- const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
- struct nouveau_device *dev = nouveau_screen(pscreen)->device;
- static bool debug_cap_printed[PIPE_CAP_LAST] = {};
+ struct nouveau_screen *screen = nouveau_screen(pscreen);
+ const uint16_t class_3d = screen->class_3d;
+ struct nouveau_device *dev = screen->device;
switch (param) {
/* non-boolean caps */
@@ -123,7 +124,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
case PIPE_CAP_MAX_TEXEL_OFFSET:
return 7;
- case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
+ case PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT:
return 128 * 1024 * 1024;
case PIPE_CAP_GLSL_FEATURE_LEVEL:
return 330;
@@ -153,7 +154,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return 1;
case PIPE_CAP_MAX_GS_INVOCATIONS:
return 0;
- case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
+ case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
return 1 << 27;
case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
return 2048;
@@ -190,24 +191,20 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_SUPPORTED_PRIM_MODES_WITH_RESTART:
case PIPE_CAP_SUPPORTED_PRIM_MODES:
- return BITFIELD_MASK(PIPE_PRIM_MAX);
+ return BITFIELD_MASK(MESA_PRIM_COUNT);
/* supported caps */
case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
case PIPE_CAP_TEXTURE_SWIZZLE:
- case PIPE_CAP_TEXTURE_SHADOW_MAP:
case PIPE_CAP_NPOT_TEXTURES:
case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
case PIPE_CAP_ANISOTROPIC_FILTER:
case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
- case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
case PIPE_CAP_DEPTH_CLIP_DISABLE:
- case PIPE_CAP_POINT_SPRITE:
case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
- case PIPE_CAP_VERTEX_SHADER_SATURATE:
case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
case PIPE_CAP_VERTEX_COLOR_CLAMPED:
@@ -216,55 +213,54 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_OCCLUSION_QUERY:
case PIPE_CAP_BLEND_EQUATION_SEPARATE:
case PIPE_CAP_INDEP_BLEND_ENABLE:
- case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
- case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
+ case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT:
+ case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
case PIPE_CAP_PRIMITIVE_RESTART:
case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
- case PIPE_CAP_TGSI_INSTANCEID:
+ case PIPE_CAP_VS_INSTANCEID:
case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
- case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
case PIPE_CAP_CONDITIONAL_RENDER:
case PIPE_CAP_TEXTURE_BARRIER:
case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
case PIPE_CAP_START_INSTANCE:
case PIPE_CAP_USER_VERTEX_BUFFERS:
case PIPE_CAP_TEXTURE_MULTISAMPLE:
- case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
- case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
+ case PIPE_CAP_FS_FINE_DERIVATIVE:
case PIPE_CAP_SAMPLER_VIEW_TARGET:
case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
case PIPE_CAP_CLIP_HALFZ:
+ case PIPE_CAP_MEMOBJ:
case PIPE_CAP_POLYGON_OFFSET_CLAMP:
case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
case PIPE_CAP_DEPTH_BOUNDS_TEST:
- case PIPE_CAP_TGSI_TXQS:
+ case PIPE_CAP_TEXTURE_QUERY_SAMPLES:
case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
- case PIPE_CAP_CLEAR_TEXTURE:
- case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
+ case PIPE_CAP_FS_FACE_IS_INTEGER_SYSVAL:
case PIPE_CAP_INVALIDATE_BUFFER:
case PIPE_CAP_STRING_MARKER:
case PIPE_CAP_CULL_DISTANCE:
- case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
- case PIPE_CAP_TGSI_MUL_ZERO_WINS:
+ case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
+ case PIPE_CAP_LEGACY_MATH_RULES:
case PIPE_CAP_TGSI_TEX_TXF_LZ:
- case PIPE_CAP_TGSI_CLOCK:
+ case PIPE_CAP_SHADER_CLOCK:
case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
- case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
- case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
case PIPE_CAP_TGSI_DIV:
- case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
- case PIPE_CAP_FLATSHADE:
- case PIPE_CAP_ALPHA_TEST:
- case PIPE_CAP_POINT_SIZE_FIXED:
- case PIPE_CAP_TWO_SIDED_COLOR:
- case PIPE_CAP_CLIP_PLANES:
- case PIPE_CAP_PACKED_STREAM_OUTPUT:
case PIPE_CAP_CLEAR_SCISSORED:
case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
case PIPE_CAP_COMPUTE:
+ case PIPE_CAP_QUERY_MEMORY_INFO:
return 1;
+
+ case PIPE_CAP_ALPHA_TEST:
+ /* nvc0 has fixed function alpha test support, but nv50 doesn't. If we
+ * don't have it, then the frontend will lower it for us.
+ */
+ return class_3d >= NVC0_3D_CLASS;
+
+ case PIPE_CAP_TEXTURE_TRANSFER_MODES:
+ return PIPE_TEXTURE_TRANSFER_BLIT;
case PIPE_CAP_SEAMLESS_CUBE_MAP:
return 1; /* class_3d >= NVA0_3D_CLASS; */
/* supported on nva0+ */
@@ -278,120 +274,17 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
return class_3d >= NVA3_3D_CLASS;
- /* unsupported caps */
- case PIPE_CAP_EMULATE_NONFIXED_PRIMITIVE_RESTART:
- case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
- case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
- case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
- case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
- case PIPE_CAP_SHADER_STENCIL_EXPORT:
- case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
- case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
- case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
- case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
- case PIPE_CAP_TGSI_TEXCOORD:
- case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
- case PIPE_CAP_TEXTURE_GATHER_SM5:
- case PIPE_CAP_FAKE_SW_MSAA:
- case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
- case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
- case PIPE_CAP_DRAW_INDIRECT:
- case PIPE_CAP_MULTI_DRAW_INDIRECT:
- case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
- case PIPE_CAP_VERTEXID_NOBASE:
- case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
- case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
- case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
- case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
- case PIPE_CAP_DRAW_PARAMETERS:
- case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
- case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
- case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
- case PIPE_CAP_GENERATE_MIPMAP:
- case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
- case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
- case PIPE_CAP_QUERY_BUFFER_OBJECT:
- case PIPE_CAP_QUERY_MEMORY_INFO:
case PIPE_CAP_PCI_GROUP:
case PIPE_CAP_PCI_BUS:
case PIPE_CAP_PCI_DEVICE:
case PIPE_CAP_PCI_FUNCTION:
- case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
- case PIPE_CAP_TGSI_VOTE:
- case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
- case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
- case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
- case PIPE_CAP_NATIVE_FENCE_FD:
- case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
- case PIPE_CAP_FBFETCH:
- case PIPE_CAP_DOUBLES:
- case PIPE_CAP_INT64:
- case PIPE_CAP_INT64_DIVMOD:
- case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
- case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
- case PIPE_CAP_TGSI_BALLOT:
- case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
- case PIPE_CAP_POST_DEPTH_COVERAGE:
- case PIPE_CAP_BINDLESS_TEXTURE:
- case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
- case PIPE_CAP_QUERY_SO_OVERFLOW:
- case PIPE_CAP_MEMOBJ:
- case PIPE_CAP_LOAD_CONSTBUF:
- case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
- case PIPE_CAP_TILE_RASTER_ORDER:
- case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
- case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
- case PIPE_CAP_CONTEXT_PRIORITY_MASK:
- case PIPE_CAP_FENCE_SIGNAL:
- case PIPE_CAP_CONSTBUF0_FLAGS:
- case PIPE_CAP_PACKED_UNIFORMS:
- case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
- case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
- case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
- case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
- case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
- case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
- case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
- case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
- case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
- case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
- case PIPE_CAP_SURFACE_SAMPLE_COUNT:
- case PIPE_CAP_TGSI_ATOMFADD:
- case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
- case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
- case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
- case PIPE_CAP_NIR_COMPACT_ARRAYS:
- case PIPE_CAP_IMAGE_LOAD_FORMATTED:
- case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
- case PIPE_CAP_ATOMIC_FLOAT_MINMAX:
- case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE:
- case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK:
- case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED:
- case PIPE_CAP_FBFETCH_COHERENT:
- case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS:
- case PIPE_CAP_TGSI_ATOMINC_WRAP:
- case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION:
- case PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE:
- case PIPE_CAP_OPENCL_INTEGER_FUNCTIONS:
+ return 0;
+
+ case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: /* potentially supported on some hw */
case PIPE_CAP_INTEGER_MULTIPLY_32X16: /* could be done */
- case PIPE_CAP_FRONTEND_NOOP:
- case PIPE_CAP_GL_SPIRV:
- case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
- case PIPE_CAP_TEXTURE_SHADOW_LOD:
- case PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED:
- case PIPE_CAP_PSIZ_CLAMPED:
- case PIPE_CAP_VIEWPORT_SWIZZLE:
- case PIPE_CAP_VIEWPORT_MASK:
- case PIPE_CAP_TEXTURE_BUFFER_SAMPLER:
- case PIPE_CAP_PREFER_REAL_BUFFER_IN_CONSTBUF0:
case PIPE_CAP_MAP_UNSYNCHRONIZED_THREAD_SAFE: /* when we fix MT stuff */
- case PIPE_CAP_ALPHA_TO_COVERAGE_DITHER_CONTROL:
- case PIPE_CAP_SHADER_ATOMIC_INT64:
- case PIPE_CAP_GLSL_ZERO_INIT:
- case PIPE_CAP_BLEND_EQUATION_ADVANCED:
- case PIPE_CAP_NO_CLIP_ON_COPY_TEX:
- case PIPE_CAP_DEVICE_PROTECTED_CONTENT:
case PIPE_CAP_NIR_IMAGES_AS_DEREF:
+ case PIPE_CAP_HARDWARE_GL_SELECT:
return 0;
case PIPE_CAP_VENDOR_ID:
@@ -409,17 +302,9 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_VIDEO_MEMORY:
return dev->vram_size >> 20;
case PIPE_CAP_UMA:
- return 0;
+ return nouveau_screen(pscreen)->is_uma;
default:
- if (!debug_cap_printed[param]) {
- debug_printf("%s: unhandled cap %d\n", __func__, param);
- debug_cap_printed[param] = true;
- }
- FALLTHROUGH;
- /* caps where we want the default value */
- case PIPE_CAP_DMABUF:
- case PIPE_CAP_THROTTLE:
return u_pipe_screen_get_param_defaults(pscreen, param);
}
}
@@ -429,8 +314,6 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen,
enum pipe_shader_type shader,
enum pipe_shader_cap param)
{
- const struct nouveau_screen *screen = nouveau_screen(pscreen);
-
switch (shader) {
case PIPE_SHADER_VERTEX:
case PIPE_SHADER_GEOMETRY:
@@ -455,7 +338,7 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen,
return 15;
case PIPE_SHADER_CAP_MAX_OUTPUTS:
return 16;
- case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
+ case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
return 65536;
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
return NV50_MAX_PIPE_CONSTBUFS;
@@ -467,7 +350,7 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen,
return 1;
case PIPE_SHADER_CAP_MAX_TEMPS:
return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE;
- case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
+ case PIPE_SHADER_CAP_CONT_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
return 1;
@@ -481,8 +364,6 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen,
return 0; /* please inline, or provide function declarations */
case PIPE_SHADER_CAP_INTEGERS:
return 1;
- case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
- return 1;
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
/* The chip could handle more sampler views than samplers */
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
@@ -491,18 +372,9 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen,
return shader == PIPE_SHADER_COMPUTE ? NV50_MAX_GLOBALS - 1 : 0;
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
return shader == PIPE_SHADER_COMPUTE ? NV50_MAX_GLOBALS - 1 : 0;
- case PIPE_SHADER_CAP_PREFERRED_IR:
- return screen->prefer_nir ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI;
- case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
- return 32;
case PIPE_SHADER_CAP_SUPPORTED_IRS:
- return (1 << PIPE_SHADER_IR_TGSI) | (1 << PIPE_SHADER_IR_NIR);
- case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
- case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
- case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
- case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
+ return 1 << PIPE_SHADER_IR_NIR;
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
- case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
return 0;
@@ -516,11 +388,19 @@ static float
nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
{
switch (param) {
+ case PIPE_CAPF_MIN_LINE_WIDTH:
+ case PIPE_CAPF_MIN_LINE_WIDTH_AA:
+ case PIPE_CAPF_MIN_POINT_SIZE:
+ case PIPE_CAPF_MIN_POINT_SIZE_AA:
+ return 1;
+ case PIPE_CAPF_POINT_SIZE_GRANULARITY:
+ case PIPE_CAPF_LINE_WIDTH_GRANULARITY:
+ return 0.1;
case PIPE_CAPF_MAX_LINE_WIDTH:
case PIPE_CAPF_MAX_LINE_WIDTH_AA:
return 10.0f;
- case PIPE_CAPF_MAX_POINT_WIDTH:
- case PIPE_CAPF_MAX_POINT_WIDTH_AA:
+ case PIPE_CAPF_MAX_POINT_SIZE:
+ case PIPE_CAPF_MAX_POINT_SIZE_AA:
return 64.0f;
case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
return 16.0f;
@@ -542,6 +422,7 @@ nv50_screen_get_compute_param(struct pipe_screen *pscreen,
enum pipe_compute_cap param, void *data)
{
struct nv50_screen *screen = nv50_screen(pscreen);
+ struct nouveau_device *dev = screen->base.device;
#define RET(x) do { \
if (data) \
@@ -559,17 +440,19 @@ nv50_screen_get_compute_param(struct pipe_screen *pscreen,
case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
RET((uint64_t []) { 512 });
case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g0-15[] */
- RET((uint64_t []) { 1ULL << 32 });
+ RET((uint64_t []) { nouveau_device_get_global_mem_size(dev) });
case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
RET((uint64_t []) { 16 << 10 });
case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
RET((uint64_t []) { 16 << 10 });
case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
RET((uint64_t []) { 4096 });
- case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
+ case PIPE_COMPUTE_CAP_SUBGROUP_SIZES:
RET((uint32_t []) { 32 });
+ case PIPE_COMPUTE_CAP_MAX_SUBGROUPS:
+ RET((uint32_t []) { 0 });
case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
- RET((uint64_t []) { 1ULL << 40 });
+ RET((uint64_t []) { nouveau_device_get_global_mem_size(dev) });
case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
RET((uint32_t []) { 0 });
case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
@@ -595,11 +478,6 @@ nv50_screen_destroy(struct pipe_screen *pscreen)
if (!nouveau_drm_screen_unref(&screen->base))
return;
- nouveau_fence_cleanup(&screen->base);
-
- if (screen->base.pushbuf)
- screen->base.pushbuf->user_priv = NULL;
-
if (screen->blitter)
nv50_blitter_destroy(screen);
if (screen->pm.prog) {
@@ -628,15 +506,19 @@ nv50_screen_destroy(struct pipe_screen *pscreen)
nouveau_object_del(&screen->sync);
nouveau_screen_fini(&screen->base);
+ simple_mtx_destroy(&screen->state_lock);
FREE(screen);
}
static void
-nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
+nv50_screen_fence_emit(struct pipe_context *pcontext, u32 *sequence,
+ struct nouveau_bo *wait)
{
- struct nv50_screen *screen = nv50_screen(pscreen);
- struct nouveau_pushbuf *push = screen->base.pushbuf;
+ struct nv50_context *nv50 = nv50_context(pcontext);
+ struct nv50_screen *screen = nv50->screen;
+ struct nouveau_pushbuf *push = nv50->base.pushbuf;
+ struct nouveau_pushbuf_refn ref = { wait, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR };
/* we need to do it after possible flush in MARK_RING */
*sequence = ++screen->base.fence.sequence;
@@ -652,6 +534,8 @@ nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence)
NV50_3D_QUERY_GET_TYPE_QUERY |
NV50_3D_QUERY_GET_QUERY_SELECT_ZERO |
NV50_3D_QUERY_GET_SHORT);
+
+ nouveau_pushbuf_refn(push, &ref, 1);
}
static u32
@@ -756,16 +640,16 @@ nv50_screen_init_hwctx(struct nv50_screen *screen)
PUSH_DATA (push, 0x3f);
BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2);
- PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
- PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2));
+ PUSH_DATAh(push, screen->code->offset + (NV50_SHADER_STAGE_VERTEX << NV50_CODE_BO_SIZE_LOG2));
+ PUSH_DATA (push, screen->code->offset + (NV50_SHADER_STAGE_VERTEX << NV50_CODE_BO_SIZE_LOG2));
BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2);
- PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
- PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2));
+ PUSH_DATAh(push, screen->code->offset + (NV50_SHADER_STAGE_FRAGMENT << NV50_CODE_BO_SIZE_LOG2));
+ PUSH_DATA (push, screen->code->offset + (NV50_SHADER_STAGE_FRAGMENT << NV50_CODE_BO_SIZE_LOG2));
BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2);
- PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
- PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2));
+ PUSH_DATAh(push, screen->code->offset + (NV50_SHADER_STAGE_GEOMETRY << NV50_CODE_BO_SIZE_LOG2));
+ PUSH_DATA (push, screen->code->offset + (NV50_SHADER_STAGE_GEOMETRY << NV50_CODE_BO_SIZE_LOG2));
BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3);
PUSH_DATAh(push, screen->tls_bo->offset);
@@ -902,8 +786,6 @@ nv50_screen_init_hwctx(struct nv50_screen *screen)
PUSH_DATA (push, 1);
BEGIN_NV04(push, NV50_3D(UNK19C0), 1);
PUSH_DATA (push, 1);
-
- PUSH_KICK (push);
}
static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
@@ -912,6 +794,7 @@ static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space,
struct nouveau_device *dev = screen->base.device;
int ret;
+ assert(tls_space % ONE_TEMP_SIZE == 0);
screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) *
ONE_TEMP_SIZE;
if (nouveau_mesa_debug)
@@ -960,45 +843,13 @@ int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space)
return 1;
}
-static const nir_shader_compiler_options nir_options = {
- .fuse_ffma16 = false, /* nir doesn't track mad vs fma */
- .fuse_ffma32 = false, /* nir doesn't track mad vs fma */
- .fuse_ffma64 = false, /* nir doesn't track mad vs fma */
- .lower_flrp32 = true,
- .lower_flrp64 = true,
- .lower_fpow = false,
- .lower_uadd_carry = true,
- .lower_usub_borrow = true,
- .lower_ffract = true,
- .lower_pack_half_2x16 = true,
- .lower_pack_unorm_2x16 = true,
- .lower_pack_snorm_2x16 = true,
- .lower_pack_unorm_4x8 = true,
- .lower_pack_snorm_4x8 = true,
- .lower_unpack_half_2x16 = true,
- .lower_unpack_unorm_2x16 = true,
- .lower_unpack_snorm_2x16 = true,
- .lower_unpack_unorm_4x8 = true,
- .lower_unpack_snorm_4x8 = true,
- .lower_extract_byte = true,
- .lower_extract_word = true,
- .lower_insert_byte = true,
- .lower_insert_word = true,
- .lower_all_io_to_temps = false,
- .lower_cs_local_index_from_id = true,
- .lower_rotate = true,
- .lower_to_scalar = true,
- .use_interpolated_input_intrinsics = true,
- .max_unroll_iterations = 32,
-};
-
static const void *
nv50_screen_get_compiler_options(struct pipe_screen *pscreen,
enum pipe_shader_ir ir,
enum pipe_shader_type shader)
{
if (ir == PIPE_SHADER_IR_NIR)
- return &nir_options;
+ return nv50_ir_nir_shader_compiler_options(NVISA_G80_CHIPSET, shader);
return NULL;
}
@@ -1019,6 +870,7 @@ nv50_screen_create(struct nouveau_device *dev)
pscreen = &screen->base.base;
pscreen->destroy = nv50_screen_destroy;
+ simple_mtx_init(&screen->state_lock, mtx_plain);
ret = nouveau_screen_init(&screen->base, dev);
if (ret) {
NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret);
@@ -1033,7 +885,6 @@ nv50_screen_create(struct nouveau_device *dev)
screen->base.sysmem_bindings |=
PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER;
- screen->base.pushbuf->user_priv = screen;
screen->base.pushbuf->rsvd_kick = 5;
chan = screen->base.channel;
@@ -1074,7 +925,7 @@ nv50_screen_create(struct nouveau_device *dev)
goto fail;
}
- nouveau_bo_map(screen->fence.bo, 0, NULL);
+ BO_MAP(&screen->base, screen->fence.bo, 0, NULL);
screen->fence.map = screen->fence.bo->map;
screen->base.fence.emit = nv50_screen_fence_emit;
screen->base.fence.update = nv50_screen_fence_update;
@@ -1217,7 +1068,8 @@ nv50_screen_create(struct nouveau_device *dev)
goto fail;
}
- nouveau_fence_new(&screen->base, &screen->base.fence.current);
+ // submit all initial state
+ PUSH_KICK(screen->base.pushbuf);
return &screen->base;
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-24 23:04:39 +0000