summaryrefslogtreecommitdiff
path: root/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/gallium/drivers/freedreno/a3xx/fd3_gmem.c')
-rw-r--r--src/gallium/drivers/freedreno/a3xx/fd3_gmem.c42
1 files changed, 21 insertions, 21 deletions
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c b/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
index e338015fc8f..b15c880195b 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
@@ -99,7 +99,7 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
else
pformat = util_format_linear(pformat);
- debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
+ assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
offset = fd_resource_offset(rsc, psurf->u.tex.level,
psurf->u.tex.first_layer);
@@ -251,7 +251,7 @@ emit_binning_workaround(struct fd_batch *batch) assert_dt
A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
- OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0.0));
+ OUT_RING(ring, A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0.0f));
OUT_PKT0(ring, REG_A3XX_VFD_INDEX_MIN, 4);
OUT_RING(ring, 0); /* VFD_INDEX_MIN */
@@ -280,12 +280,12 @@ emit_binning_workaround(struct fd_batch *batch) assert_dt
fd_wfi(batch, ring);
OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
- OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(0.0));
- OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(1.0));
- OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(0.0));
- OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(1.0));
- OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
- OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
+ OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(0.0f));
+ OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(1.0f));
+ OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(0.0f));
+ OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(1.0f));
+ OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0f));
+ OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0f));
OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
OUT_RING(ring, A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE |
@@ -350,7 +350,7 @@ emit_gmem2mem_surf(struct fd_batch *batch,
fd_resource_offset(rsc, psurf->u.tex.level, psurf->u.tex.first_layer);
uint32_t pitch = fd_resource_pitch(rsc, psurf->u.tex.level);
- debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
+ assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
OUT_PKT0(ring, REG_A3XX_RB_COPY_CONTROL, 4);
OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
@@ -420,12 +420,12 @@ fd3_emit_tile_gmem2mem(struct fd_batch *batch,
fd_wfi(batch, ring);
OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
- OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)pfb->width / 2.0 - 0.5));
- OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)pfb->width / 2.0));
- OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)pfb->height / 2.0 - 0.5));
- OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)pfb->height / 2.0));
- OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
- OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
+ OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)pfb->width / 2.0f - 0.5f));
+ OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)pfb->width / 2.0f));
+ OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)pfb->height / 2.0f - 0.5f));
+ OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)pfb->height / 2.0f));
+ OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0f));
+ OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0f));
OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 1);
OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
@@ -627,12 +627,12 @@ fd3_emit_tile_mem2gmem(struct fd_batch *batch,
fd_wfi(batch, ring);
OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
- OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)bin_w / 2.0 - 0.5));
- OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)bin_w / 2.0));
- OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)bin_h / 2.0 - 0.5));
- OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)bin_h / 2.0));
- OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0));
- OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0));
+ OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET((float)bin_w / 2.0f - 0.5f));
+ OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE((float)bin_w / 2.0f));
+ OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET((float)bin_h / 2.0f - 0.5f));
+ OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-(float)bin_h / 2.0f));
+ OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(0.0f));
+ OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(1.0f));
OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |