diff options
Diffstat (limited to 'src/freedreno/vulkan/tu_clear_blit.c')
| -rw-r--r-- | src/freedreno/vulkan/tu_clear_blit.c | 38 |
1 files changed, 35 insertions, 3 deletions
diff --git a/src/freedreno/vulkan/tu_clear_blit.c b/src/freedreno/vulkan/tu_clear_blit.c index a3168d5fbe5..6caa31beb95 100644 --- a/src/freedreno/vulkan/tu_clear_blit.c +++ b/src/freedreno/vulkan/tu_clear_blit.c @@ -944,9 +944,15 @@ r3d_src_gmem(struct tu_cmd_buffer *cmd, uint32_t desc[A6XX_TEX_CONST_DWORDS]; memcpy(desc, iview->view.descriptor, sizeof(desc)); - /* patch the format so that depth/stencil get the right format */ - desc[0] &= ~A6XX_TEX_CONST_0_FMT__MASK; - desc[0] |= A6XX_TEX_CONST_0_FMT(tu6_format_texture(format, TILE6_2).fmt); + /* patch the format so that depth/stencil get the right format and swizzle */ + desc[0] &= ~(A6XX_TEX_CONST_0_FMT__MASK | + A6XX_TEX_CONST_0_SWIZ_X__MASK | A6XX_TEX_CONST_0_SWIZ_Y__MASK | + A6XX_TEX_CONST_0_SWIZ_Z__MASK | A6XX_TEX_CONST_0_SWIZ_W__MASK); + desc[0] |= A6XX_TEX_CONST_0_FMT(tu6_format_texture(format, TILE6_2).fmt) | + A6XX_TEX_CONST_0_SWIZ_X(A6XX_TEX_X) | + A6XX_TEX_CONST_0_SWIZ_Y(A6XX_TEX_Y) | + A6XX_TEX_CONST_0_SWIZ_Z(A6XX_TEX_Z) | + A6XX_TEX_CONST_0_SWIZ_W(A6XX_TEX_W); /* patched for gmem */ desc[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK | A6XX_TEX_CONST_0_TILE_MODE__MASK); @@ -2687,6 +2693,7 @@ tu_clear_sysmem_attachment(struct tu_cmd_buffer *cmd, */ if (vk_format_is_depth_or_stencil(attachment->format)) { tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS); + tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_DEPTH_TS); tu6_emit_event_write(cmd, cs, PC_CCU_INVALIDATE_DEPTH); } else { tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS); @@ -2887,6 +2894,17 @@ store_3d_blit(struct tu_cmd_buffer *cmd, uint32_t gmem_offset, uint32_t cpp) { + /* RB_BIN_CONTROL/GRAS_BIN_CONTROL are normally only set once and they + * aren't set until we know whether we're HW binning or not, and we want to + * avoid a dependence on that here to be able to store attachments before + * the end of the renderpass in the future. Use the scratch space to + * save/restore them dynamically. + */ + tu_cs_emit_pkt7(cs, CP_REG_TO_SCRATCH, 1); + tu_cs_emit(cs, CP_REG_TO_SCRATCH_0_REG(REG_A6XX_RB_BIN_CONTROL) | + CP_REG_TO_SCRATCH_0_SCRATCH(0) | + CP_REG_TO_SCRATCH_0_CNT(1 - 1)); + r3d_setup(cmd, cs, format, VK_IMAGE_ASPECT_COLOR_BIT, 0, false, iview->view.ubwc_enabled, dst_samples); @@ -2907,6 +2925,9 @@ store_3d_blit(struct tu_cmd_buffer *cmd, /* sync GMEM writes with CACHE. */ tu6_emit_event_write(cmd, cs, CACHE_INVALIDATE); + /* Wait for CACHE_INVALIDATE to land */ + tu_cs_emit_wfi(cs); + r3d_run(cmd, cs); /* Draws write to the CCU, unlike CP_EVENT_WRITE::BLIT which writes to @@ -2915,6 +2936,17 @@ store_3d_blit(struct tu_cmd_buffer *cmd, * writes to depth images as a color RT, so there's no need to flush depth. */ tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS); + + /* Restore RB_BIN_CONTROL/GRAS_BIN_CONTROL saved above. */ + tu_cs_emit_pkt7(cs, CP_SCRATCH_TO_REG, 1); + tu_cs_emit(cs, CP_SCRATCH_TO_REG_0_REG(REG_A6XX_RB_BIN_CONTROL) | + CP_SCRATCH_TO_REG_0_SCRATCH(0) | + CP_SCRATCH_TO_REG_0_CNT(1 - 1)); + + tu_cs_emit_pkt7(cs, CP_SCRATCH_TO_REG, 1); + tu_cs_emit(cs, CP_SCRATCH_TO_REG_0_REG(REG_A6XX_GRAS_BIN_CONTROL) | + CP_SCRATCH_TO_REG_0_SCRATCH(0) | + CP_SCRATCH_TO_REG_0_CNT(1 - 1)); } void |