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-rw-r--r--src/mesa/drivers/dri/r600/defaultendian.h4
-rw-r--r--src/mesa/drivers/dri/r600/r600_blit.c117
-rw-r--r--src/mesa/drivers/dri/r600/r600_blit_shaders.h4
-rw-r--r--src/mesa/drivers/dri/r600/r600_emit.c16
-rw-r--r--src/mesa/drivers/dri/r600/r600_texstate.c149
-rw-r--r--src/mesa/drivers/dri/r600/r700_assembler.c11
-rw-r--r--src/mesa/drivers/dri/r600/r700_assembler.h133
-rw-r--r--src/mesa/drivers/dri/r600/r700_chip.c10
-rw-r--r--src/mesa/drivers/dri/r600/r700_render.c19
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_common.c2
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_span.c93
11 files changed, 508 insertions, 50 deletions
diff --git a/src/mesa/drivers/dri/r600/defaultendian.h b/src/mesa/drivers/dri/r600/defaultendian.h
index 32caf32cd2e..75bd61c3cd4 100644
--- a/src/mesa/drivers/dri/r600/defaultendian.h
+++ b/src/mesa/drivers/dri/r600/defaultendian.h
@@ -29,8 +29,8 @@
#define _DEFINEENDIAN_H_
//We have to choose a reg bits orientation if there is no compile flag for it.
-#if defined(LITTLEENDIAN_CPU)
-#elif defined(BIGENDIAN_CPU)
+#ifdef MESA_BIG_ENDIAN
+#define BIGENDIAN_CPU
#else
#define LITTLEENDIAN_CPU
#endif
diff --git a/src/mesa/drivers/dri/r600/r600_blit.c b/src/mesa/drivers/dri/r600/r600_blit.c
index 31c32d62f9a..2d47afdcbbf 100644
--- a/src/mesa/drivers/dri/r600/r600_blit.c
+++ b/src/mesa/drivers/dri/r600/r600_blit.c
@@ -94,17 +94,17 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
{
uint32_t cb_color0_base, cb_color0_size = 0, cb_color0_info = 0, cb_color0_view = 0;
int id = 0;
- uint32_t comp_swap, format;
+ uint32_t endian, comp_swap, format;
BATCH_LOCALS(&context->radeon);
cb_color0_base = dst_offset / 256;
+ endian = ENDIAN_NONE;
SETfield(cb_color0_size, (nPitchInPixel / 8) - 1,
PITCH_TILE_MAX_shift, PITCH_TILE_MAX_mask);
SETfield(cb_color0_size, ((nPitchInPixel * h) / 64) - 1,
SLICE_TILE_MAX_shift, SLICE_TILE_MAX_mask);
- SETfield(cb_color0_info, ENDIAN_NONE, ENDIAN_shift, ENDIAN_mask);
SETfield(cb_color0_info, ARRAY_LINEAR_GENERAL,
CB_COLOR0_INFO__ARRAY_MODE_shift, CB_COLOR0_INFO__ARRAY_MODE_mask);
@@ -112,24 +112,36 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
switch(mesa_format) {
case MESA_FORMAT_RGBA8888:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_8_8_8_8;
comp_swap = SWAP_STD_REV;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_SIGNED_RGBA8888:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_8_8_8_8;
comp_swap = SWAP_STD_REV;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_SNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_RGBA8888_REV:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_8_8_8_8;
comp_swap = SWAP_STD;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_SIGNED_RGBA8888_REV:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_8_8_8_8;
comp_swap = SWAP_STD;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
@@ -137,6 +149,9 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
break;
case MESA_FORMAT_ARGB8888:
case MESA_FORMAT_XRGB8888:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_8_8_8_8;
comp_swap = SWAP_ALT;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
@@ -144,54 +159,81 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
break;
case MESA_FORMAT_ARGB8888_REV:
case MESA_FORMAT_XRGB8888_REV:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_8_8_8_8;
comp_swap = SWAP_ALT_REV;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_RGB565:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
+ comp_swap = SWAP_STD_REV;
format = COLOR_5_6_5;
- comp_swap = SWAP_STD_REV;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_RGB565_REV:
- format = COLOR_5_6_5;
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
comp_swap = SWAP_STD;
+ format = COLOR_5_6_5;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_ARGB4444:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_4_4_4_4;
comp_swap = SWAP_ALT;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_ARGB4444_REV:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_4_4_4_4;
comp_swap = SWAP_ALT_REV;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_ARGB1555:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_1_5_5_5;
comp_swap = SWAP_ALT;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_ARGB1555_REV:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_1_5_5_5;
comp_swap = SWAP_ALT_REV;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_AL88:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_8_8;
comp_swap = SWAP_STD;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_AL88_REV:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_8_8;
comp_swap = SWAP_STD_REV;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
@@ -223,6 +265,9 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_RGBA_FLOAT32:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_32_32_32_32_FLOAT;
comp_swap = SWAP_STD;
SETbit(cb_color0_info, BLEND_FLOAT32_bit);
@@ -230,12 +275,18 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_RGBA_FLOAT16:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_16_16_16_16_FLOAT;
comp_swap = SWAP_STD;
CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_ALPHA_FLOAT32:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_32_FLOAT;
comp_swap = SWAP_ALT_REV;
SETbit(cb_color0_info, BLEND_FLOAT32_bit);
@@ -243,12 +294,18 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_ALPHA_FLOAT16:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_16_FLOAT;
comp_swap = SWAP_ALT_REV;
CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_LUMINANCE_FLOAT32:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_32_FLOAT;
comp_swap = SWAP_ALT;
SETbit(cb_color0_info, BLEND_FLOAT32_bit);
@@ -256,12 +313,18 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_LUMINANCE_FLOAT16:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_16_FLOAT;
comp_swap = SWAP_ALT;
CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_32_32_FLOAT;
comp_swap = SWAP_ALT_REV;
SETbit(cb_color0_info, BLEND_FLOAT32_bit);
@@ -269,12 +332,18 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_16_16_FLOAT;
comp_swap = SWAP_ALT_REV;
CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_INTENSITY_FLOAT32: /* X, X, X, X */
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_32_FLOAT;
comp_swap = SWAP_STD;
SETbit(cb_color0_info, BLEND_FLOAT32_bit);
@@ -282,6 +351,9 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
SETfield(cb_color0_info, NUMBER_FLOAT, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_INTENSITY_FLOAT16: /* X, X, X, X */
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_16_FLOAT;
comp_swap = SWAP_STD;
CLEARbit(cb_color0_info, SOURCE_FORMAT_bit);
@@ -289,6 +361,9 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
break;
case MESA_FORMAT_X8_Z24:
case MESA_FORMAT_S8_Z24:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_8_24;
comp_swap = SWAP_STD;
SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
@@ -297,6 +372,9 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_Z24_S8:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_24_8;
comp_swap = SWAP_STD;
SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
@@ -305,6 +383,9 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_Z16:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_16;
comp_swap = SWAP_STD;
SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
@@ -313,6 +394,9 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_Z32:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_32;
comp_swap = SWAP_STD;
SETfield(cb_color0_info, ARRAY_1D_TILED_THIN1,
@@ -321,12 +405,18 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
SETfield(cb_color0_info, NUMBER_UNORM, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_SARGB8:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN32;
+#endif
format = COLOR_8_8_8_8;
comp_swap = SWAP_ALT;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
SETfield(cb_color0_info, NUMBER_SRGB, NUMBER_TYPE_shift, NUMBER_TYPE_mask);
break;
case MESA_FORMAT_SLA8:
+#ifdef MESA_BIG_ENDIAN
+ endian = ENDIAN_8IN16;
+#endif
format = COLOR_8_8;
comp_swap = SWAP_ALT_REV;
SETbit(cb_color0_info, SOURCE_FORMAT_bit);
@@ -348,6 +438,7 @@ set_render_target(context_t *context, struct radeon_bo *bo, gl_format mesa_forma
if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
CLEARbit(cb_color0_info, BLEND_FLOAT32_bit);
+ SETfield(cb_color0_info, endian, ENDIAN_shift, ENDIAN_mask);
SETfield(cb_color0_info, format, CB_COLOR0_INFO__FORMAT_shift,
CB_COLOR0_INFO__FORMAT_mask);
SETfield(cb_color0_info, comp_swap, COMP_SWAP_shift, COMP_SWAP_mask);
@@ -426,10 +517,10 @@ static inline void load_shaders(struct gl_context * ctx)
shader = context->blit_bo->ptr;
for(i=0; i<sizeof(r6xx_vs)/4; i++) {
- shader[128+i] = r6xx_vs[i];
+ shader[128+i] = CPU_TO_LE32(r6xx_vs[i]);
}
for(i=0; i<sizeof(r6xx_ps)/4; i++) {
- shader[256+i] = r6xx_ps[i];
+ shader[256+i] = CPU_TO_LE32(r6xx_ps[i]);
}
radeon_bo_unmap(context->blit_bo);
@@ -521,6 +612,8 @@ static inline void
set_vtx_resource(context_t *context)
{
struct radeon_bo *bo = context->blit_bo;
+ uint32_t sq_vtx_constant_word2 = 0;
+
BATCH_LOCALS(&context->radeon);
BEGIN_BATCH_NO_AUTOSTATE(6);
@@ -543,13 +636,19 @@ set_vtx_resource(context_t *context)
else
r700SyncSurf(context, bo, RADEON_GEM_DOMAIN_GTT, 0, VC_ACTION_ENA_bit);
+ sq_vtx_constant_word2 = 0
+#ifdef MESA_BIG_ENDIAN
+ | (SQ_ENDIAN_8IN32 << SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift)
+#endif
+ | (16 << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift);
+
BEGIN_BATCH_NO_AUTOSTATE(9 + 2);
R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
R600_OUT_BATCH(SQ_FETCH_RESOURCE_VS_OFFSET * FETCH_RESOURCE_STRIDE);
R600_OUT_BATCH(0);
R600_OUT_BATCH(48 - 1);
- R600_OUT_BATCH(16 << SQ_VTX_CONSTANT_WORD2_0__STRIDE_shift);
+ R600_OUT_BATCH(sq_vtx_constant_word2);
R600_OUT_BATCH(1 << MEM_REQUEST_SIZE_shift);
R600_OUT_BATCH(0);
R600_OUT_BATCH(0);
@@ -670,11 +769,11 @@ set_tex_resource(context_t * context,
SETfield(sq_tex_resource1, FMT_8_8_8_8,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
- SETfield(sq_tex_resource4, SQ_SEL_1,
+ SETfield(sq_tex_resource4, SQ_SEL_Y,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(sq_tex_resource4, SQ_SEL_Z,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(sq_tex_resource4, SQ_SEL_W,
+ SETfield(sq_tex_resource4, SQ_SEL_1,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(sq_tex_resource4, SQ_SEL_X,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
diff --git a/src/mesa/drivers/dri/r600/r600_blit_shaders.h b/src/mesa/drivers/dri/r600/r600_blit_shaders.h
index 492dde96368..2124f7673d7 100644
--- a/src/mesa/drivers/dri/r600/r600_blit_shaders.h
+++ b/src/mesa/drivers/dri/r600/r600_blit_shaders.h
@@ -10,7 +10,11 @@ const uint32_t r6xx_vs[] =
0x00000000,
0x3c000000, // SQ_VTX_INST_FETCH BUFFER_ID(0) MEGA_FETCH_COUNT(16)
0x68cd1000, // DST_GPR(0) DST_SWZ: XYZW DATA_FORMAT(35) SQ_NUM_FORMAT_SCALED SQ_FORMAT_COMP_SIGNED
+#ifdef MESA_BIG_ENDIAN
+ 0x000a0000, // ENDIAN_SWAP(SQ_ENDIAN_8IN32) MEGA_FETCH(1)
+#else
0x00080000, // ENDIAN_SWAP(SQ_ENDIAN_NONE) MEGA_FETCH(1)
+#endif
0x00000000, // VTX_DWORD_PAD
};
diff --git a/src/mesa/drivers/dri/r600/r600_emit.c b/src/mesa/drivers/dri/r600/r600_emit.c
index 53ece9a3505..c6916ed98a3 100644
--- a/src/mesa/drivers/dri/r600/r600_emit.c
+++ b/src/mesa/drivers/dri/r600/r600_emit.c
@@ -100,14 +100,17 @@ GLboolean r600EmitShaderConsts(struct gl_context * ctx,
int sizeinBYTE)
{
struct radeon_bo * pbo = (struct radeon_bo *)constbo;
- uint8_t *out;
+ uint32_t *out;
+ int i;
radeon_bo_map(pbo, 1);
- out = (uint8_t*)(pbo->ptr);
- out = (uint8_t*)ADD_POINTERS(pbo->ptr, bo_offset);
+ out = (uint32_t*)(pbo->ptr);
+ out = (uint32_t*)ADD_POINTERS(pbo->ptr, bo_offset);
- memcpy(out, data, sizeinBYTE);
+ for(i = 0; i < sizeinBYTE / 4; i++) {
+ out[i] = CPU_TO_LE32(*((uint32_t *)data + i));
+ }
radeon_bo_unmap(pbo);
@@ -123,6 +126,7 @@ GLboolean r600EmitShader(struct gl_context * ctx,
radeonContextPtr radeonctx = RADEON_CONTEXT(ctx);
struct radeon_bo * pbo;
uint32_t *out;
+ int i;
shader_again_alloc:
pbo = radeon_bo_open(radeonctx->radeonScreen->bom,
0,
@@ -154,7 +158,9 @@ shader_again_alloc:
out = (uint32_t*)(pbo->ptr);
- memcpy(out, data, sizeinDWORD * 4);
+ for(i = 0; i < sizeinDWORD; i++) {
+ out[i] = CPU_TO_LE32(*((uint32_t *)data + i));
+ }
radeon_bo_unmap(pbo);
diff --git a/src/mesa/drivers/dri/r600/r600_texstate.c b/src/mesa/drivers/dri/r600/r600_texstate.c
index 3568a5515be..949db29c189 100644
--- a/src/mesa/drivers/dri/r600/r600_texstate.c
+++ b/src/mesa/drivers/dri/r600/r600_texstate.c
@@ -109,6 +109,16 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
@@ -117,6 +127,7 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888) {
SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED,
FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
@@ -133,6 +144,16 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
@@ -141,6 +162,7 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
if (mesa_format == MESA_FORMAT_SIGNED_RGBA8888_REV) {
SETfield(t->SQ_TEX_RESOURCE4, SQ_FORMAT_COMP_SIGNED,
FORMAT_COMP_X_shift, FORMAT_COMP_X_mask);
@@ -156,6 +178,16 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
@@ -164,11 +196,22 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_XRGB8888:
SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
@@ -177,24 +220,46 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_XRGB8888_REV:
SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
- SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_ARGB8888_REV:
SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8_8,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
@@ -203,11 +268,22 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_RGB888:
SETfield(t->SQ_TEX_RESOURCE1, FMT_8_8_8,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
@@ -216,11 +292,22 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_RGB565:
SETfield(t->SQ_TEX_RESOURCE1, FMT_5_6_5,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
@@ -229,11 +316,23 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
+
break;
case MESA_FORMAT_RGB565_REV:
SETfield(t->SQ_TEX_RESOURCE1, FMT_5_6_5,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
@@ -242,11 +341,22 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_1,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_ARGB4444:
SETfield(t->SQ_TEX_RESOURCE1, FMT_4_4_4_4,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
@@ -255,11 +365,21 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_ARGB4444_REV:
SETfield(t->SQ_TEX_RESOURCE1, FMT_4_4_4_4,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
@@ -268,11 +388,21 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_ARGB1555:
SETfield(t->SQ_TEX_RESOURCE1, FMT_1_5_5_5,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
@@ -281,11 +411,21 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_ARGB1555_REV:
SETfield(t->SQ_TEX_RESOURCE1, FMT_1_5_5_5,
SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_shift, SQ_TEX_RESOURCE_WORD1_0__DATA_FORMAT_mask);
-
+#ifdef MESA_BIG_ENDIAN
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Y_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
+ SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_W,
+ SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#else
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Y,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_X_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_Z,
@@ -294,6 +434,7 @@ static GLboolean r600GetTexFormat(struct gl_texture_object *tObj, gl_format mesa
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_Z_mask);
SETfield(t->SQ_TEX_RESOURCE4, SQ_SEL_X,
SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_shift, SQ_TEX_RESOURCE_WORD4_0__DST_SEL_W_mask);
+#endif
break;
case MESA_FORMAT_AL88:
case MESA_FORMAT_AL88_REV: /* TODO : Check this. */
diff --git a/src/mesa/drivers/dri/r600/r700_assembler.c b/src/mesa/drivers/dri/r600/r700_assembler.c
index 4ed37033902..216ff0b941c 100644
--- a/src/mesa/drivers/dri/r600/r700_assembler.c
+++ b/src/mesa/drivers/dri/r600/r700_assembler.c
@@ -1188,7 +1188,12 @@ GLboolean EG_assemble_vfetch_instruction(r700_AssemblerBase* pAsm,
SETfield(vfetch_instruction_ptr->m_Word2.val, 0,
EG_VTX_WORD2__OFFSET_shift,
EG_VTX_WORD2__OFFSET_mask);
- SETfield(vfetch_instruction_ptr->m_Word2.val, SQ_ENDIAN_NONE,
+ SETfield(vfetch_instruction_ptr->m_Word2.val,
+#ifdef MESA_BIG_ENDIAN
+ SQ_ENDIAN_8IN32,
+#else
+ SQ_ENDIAN_NONE,
+#endif
EG_VTX_WORD2__ENDIAN_SWAP_shift,
EG_VTX_WORD2__ENDIAN_SWAP_mask);
SETfield(vfetch_instruction_ptr->m_Word2.val, 0,
@@ -1294,7 +1299,11 @@ GLboolean assemble_vfetch_instruction2(r700_AssemblerBase* pAsm,
vfetch_instruction_ptr->m_Word1.f.use_const_fields = 1;
vfetch_instruction_ptr->m_Word1.f.data_format = data_format;
+#ifdef MESA_BIG_ENDIAN
+ vfetch_instruction_ptr->m_Word2.f.endian_swap = SQ_ENDIAN_8IN32;
+#else
vfetch_instruction_ptr->m_Word2.f.endian_swap = SQ_ENDIAN_NONE;
+#endif
if(1 == _signed)
{
diff --git a/src/mesa/drivers/dri/r600/r700_assembler.h b/src/mesa/drivers/dri/r600/r700_assembler.h
index c7c7ab2d4ff..8a9ccd1c4ec 100644
--- a/src/mesa/drivers/dri/r600/r700_assembler.h
+++ b/src/mesa/drivers/dri/r600/r700_assembler.h
@@ -130,6 +130,27 @@ typedef unsigned int BITS;
typedef struct PVSDSTtag
{
+#ifdef MESA_BIG_ENDIAN
+ BITS addrmode1:1; //32
+ BITS addrmode0:1; //31 //29
+
+ BITS dualop:1; // 30 //26
+
+ BITS op3:1; // 29 Represents *_OP3_* ALU opcode
+
+ BITS writew:1; //28
+ BITS writez:1;
+ BITS writey:1;
+ BITS writex:1;
+
+ BITS reg:10; //24 //20
+ BITS rtype:3;
+
+ BITS pred_inv :1; //11 //8
+ BITS predicated:1; //10 //8
+ BITS math:1;
+ BITS opcode:8; //(:6) //@@@ really should be 10 bits for OP2
+#else
BITS opcode:8; //(:6) //@@@ really should be 10 bits for OP2
BITS math:1;
BITS predicated:1; //10 //8
@@ -149,17 +170,41 @@ typedef struct PVSDSTtag
BITS addrmode0:1; //31 //29
BITS addrmode1:1; //32
+#endif
} PVSDST;
typedef struct PVSINSTtag
{
+#ifdef MESA_BIG_ENDIAN
+ BITS index_mode :3;
+ BITS SaturateMode :2;
+ BITS literal_slots :2;
+#else
BITS literal_slots :2;
BITS SaturateMode :2;
BITS index_mode :3;
+#endif
} PVSINST;
typedef struct PVSSRCtag
{
+#ifdef MESA_BIG_ENDIAN
+ BITS addrmode1:1; //32
+ //BITS addrsel:2;
+ BITS negw:1; //31
+ BITS negz:1;
+ BITS negy:1;
+ BITS negx:1;
+ BITS abs:1;
+
+ BITS swizzlew:3; //26
+ BITS swizzlez:3;
+ BITS swizzley:3;
+ BITS swizzlex:3;
+ BITS reg:10; //14 (8)
+ BITS addrmode0:1;
+ BITS rtype:3;
+#else
BITS rtype:3;
BITS addrmode0:1;
BITS reg:10; //14 (8)
@@ -175,10 +220,24 @@ typedef struct PVSSRCtag
BITS negw:1; //31
//BITS addrsel:2;
BITS addrmode1:1; //32
+#endif
} PVSSRC;
typedef struct PVSMATHtag
{
+#ifdef MESA_BIG_ENDIAN
+ BITS spare2:3;
+ BITS dstcomp:2; // select dest component
+ BITS negy:1;
+ BITS negx:1;
+ BITS opcode:4;
+ BITS dstoff:2; // 2 bits of dest offset into alt ram
+ BITS swizzley:3;
+ BITS swizzlex:3;
+ BITS reg:8;
+ BITS spare:1;
+ BITS rtype:4;
+#else
BITS rtype:4;
BITS spare:1;
BITS reg:8;
@@ -190,6 +249,7 @@ typedef struct PVSMATHtag
BITS negy:1;
BITS dstcomp:2; // select dest component
BITS spare2:3;
+#endif
} PVSMATH;
typedef union PVSDWORDtag
@@ -204,6 +264,34 @@ typedef union PVSDWORDtag
typedef struct VAP_OUT_VTX_FMT_0tag
{
+#ifdef MESA_BIG_ENDIAN
+ BITS resvd1:12; // 20
+
+ BITS viewport_index:1; // 19
+ BITS kill_flag:1;
+ BITS rta_index:1; // shares same channel as kill_flag
+ BITS edge_flag:1;
+ BITS point_size:1; // 15
+
+ BITS depth:1; // 14
+
+ BITS normal:1;
+
+ BITS color7:1;
+ BITS color6:1;
+ BITS color5:1;
+ BITS color4:1;
+ BITS color3:1;
+ BITS color2:1;
+ BITS color1:1;
+ BITS color0:1;
+
+ BITS pos_param:1; // 4
+ BITS clip_dist1:1;
+ BITS clip_dist0:1;
+ BITS misc:1;
+ BITS pos:1; // 0
+#else
BITS pos:1; // 0
BITS misc:1;
BITS clip_dist0:1;
@@ -230,10 +318,23 @@ typedef struct VAP_OUT_VTX_FMT_0tag
BITS viewport_index:1; // 19
BITS resvd1:12; // 20
+#endif
} VAP_OUT_VTX_FMT_0;
typedef struct VAP_OUT_VTX_FMT_1tag
{
+#ifdef MESA_BIG_ENDIAN
+ BITS resvd:8;
+
+ BITS tex7comp:3;
+ BITS tex6comp:3;
+ BITS tex5comp:3;
+ BITS tex4comp:3;
+ BITS tex3comp:3;
+ BITS tex2comp:3;
+ BITS tex1comp:3;
+ BITS tex0comp:3;
+#else
BITS tex0comp:3;
BITS tex1comp:3;
BITS tex2comp:3;
@@ -244,10 +345,23 @@ typedef struct VAP_OUT_VTX_FMT_1tag
BITS tex7comp:3;
BITS resvd:8;
+#endif
} VAP_OUT_VTX_FMT_1;
typedef struct VAP_OUT_VTX_FMT_2tag
{
+#ifdef MESA_BIG_ENDIAN
+ BITS resvd:8;
+
+ BITS tex15comp:3;
+ BITS tex14comp:3;
+ BITS tex13comp:3;
+ BITS tex12comp:3;
+ BITS tex11comp:3;
+ BITS tex10comp:3;
+ BITS tex9comp:3;
+ BITS tex8comp:3;
+#else
BITS tex8comp :3;
BITS tex9comp :3;
BITS tex10comp:3;
@@ -258,10 +372,28 @@ typedef struct VAP_OUT_VTX_FMT_2tag
BITS tex15comp:3;
BITS resvd:8;
+#endif
} VAP_OUT_VTX_FMT_2;
typedef struct OUT_FRAGMENT_FMT_0tag
{
+#ifdef MESA_BIG_ENDIAN
+ BITS resvd1:20;
+
+ BITS mask:1;
+ BITS coverage_to_mask:1;
+ BITS stencil_ref:1;
+ BITS depth:1;
+
+ BITS color7:1;
+ BITS color6:1;
+ BITS color5:1;
+ BITS color4:1;
+ BITS color3:1;
+ BITS color2:1;
+ BITS color1:1;
+ BITS color0:1;
+#else
BITS color0:1;
BITS color1:1;
BITS color2:1;
@@ -277,6 +409,7 @@ typedef struct OUT_FRAGMENT_FMT_0tag
BITS mask:1;
BITS resvd1:20;
+#endif
} OUT_FRAGMENT_FMT_0;
typedef enum CF_CLAUSE_TYPE
diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index 7980c449e02..10fa3f9762b 100644
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -202,7 +202,15 @@ static void r700SetupVTXConstants(struct gl_context * ctx,
SETfield(uSQ_VTX_CONSTANT_WORD2_0, GetSurfaceFormat(pStreamDesc->type, pStreamDesc->size, NULL),
SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_shift,
SQ_VTX_CONSTANT_WORD2_0__DATA_FORMAT_mask); /* TODO : trace back api for initial data type, not only GL_FLOAT */
-
+ SETfield(uSQ_VTX_CONSTANT_WORD2_0,
+#ifdef MESA_BIG_ENDIAN
+ SQ_ENDIAN_8IN32,
+#else
+ SQ_ENDIAN_NONE,
+#endif
+ SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_shift,
+ SQ_VTX_CONSTANT_WORD2_0__ENDIAN_SWAP_mask);
+
if(GL_TRUE == pStreamDesc->normalize)
{
SETfield(uSQ_VTX_CONSTANT_WORD2_0, SQ_NUM_FORMAT_NORM,
diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c
index bb09980ed88..2bd3b62bfdb 100644
--- a/src/mesa/drivers/dri/r600/r700_render.c
+++ b/src/mesa/drivers/dri/r600/r700_render.c
@@ -276,6 +276,16 @@ static void r700RunRenderPrimitive(struct gl_context * ctx, int start, int end,
SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
}
+ /* 16-bit indexes are packed in a 32-bit value */
+ SETfield(vgt_index_type,
+#if MESA_BIG_ENDIAN
+ VGT_DMA_SWAP_32_BIT,
+#else
+ VGT_DMA_SWAP_NONE,
+#endif
+ SWAP_MODE_shift, SWAP_MODE_mask);
+
+
vgt_num_indices = num_indices;
SETfield(vgt_draw_initiator, DI_SRC_SEL_DMA, SOURCE_SELECT_shift, SOURCE_SELECT_mask);
SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask);
@@ -348,6 +358,15 @@ static void r700RunRenderPrimitiveImmediate(struct gl_context * ctx, int start,
SETfield(vgt_index_type, DI_INDEX_SIZE_16_BIT, INDEX_TYPE_shift, INDEX_TYPE_mask);
}
+ /* 16-bit indexes are packed in a 32-bit value */
+ SETfield(vgt_index_type,
+#if MESA_BIG_ENDIAN
+ VGT_DMA_SWAP_32_BIT,
+#else
+ VGT_DMA_SWAP_NONE,
+#endif
+ SWAP_MODE_shift, SWAP_MODE_mask);
+
vgt_num_indices = num_indices;
SETfield(vgt_draw_initiator, DI_MAJOR_MODE_0, MAJOR_MODE_shift, MAJOR_MODE_mask);
diff --git a/src/mesa/drivers/dri/radeon/radeon_common.c b/src/mesa/drivers/dri/radeon/radeon_common.c
index 0d73c0e3b1b..bfc307ca987 100644
--- a/src/mesa/drivers/dri/radeon/radeon_common.c
+++ b/src/mesa/drivers/dri/radeon/radeon_common.c
@@ -966,7 +966,7 @@ static void radeon_print_state_atom(radeonContextPtr radeon, struct radeon_state
fprintf(stderr, " emit %s %d/%d\n", state->name, dwords, state->cmd_size);
- if (radeon_is_debug_enabled(RADEON_STATE, RADEON_TRACE)) {
+ if (state->cmd && radeon_is_debug_enabled(RADEON_STATE, RADEON_TRACE)) {
if (dwords > state->cmd_size)
dwords = state->cmd_size;
for (i = 0; i < dwords;) {
diff --git a/src/mesa/drivers/dri/radeon/radeon_span.c b/src/mesa/drivers/dri/radeon/radeon_span.c
index caf3f253d2a..8c6f2e49a5c 100644
--- a/src/mesa/drivers/dri/radeon/radeon_span.c
+++ b/src/mesa/drivers/dri/radeon/radeon_span.c
@@ -50,6 +50,17 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define DBG 0
+#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && BYTE_ORDER == BIG_ENDIAN
+#if defined(__linux__)
+#include <byteswap.h>
+#define CPU_TO_LE16( x ) bswap_16( x )
+#define LE16_TO_CPU( x ) bswap_16( x )
+#endif /* __linux__ */
+#else
+#define CPU_TO_LE16( x ) ( x )
+#define LE16_TO_CPU( x ) ( x )
+#endif
+
static void radeonSetSpanFunctions(struct radeon_renderbuffer *rrb);
@@ -579,7 +590,11 @@ static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb,
#define TAG(x) radeon##x##_RGB565
#define TAG2(x,y) radeon##x##_RGB565##y
#if defined(RADEON_R600)
-#define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off)
+#define GET_VALUE(_x, _y) (LE16_TO_CPU(*(GLushort*)(r600_ptr_color(rrb, _x + x_off, _y + y_off))))
+#define PUT_VALUE(_x, _y, d) { \
+ GLushort *_ptr = (GLushort*)r600_ptr_color( rrb, _x + x_off, _y + y_off ); \
+ *_ptr = CPU_TO_LE16(d); \
+} while (0)
#else
#define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off)
#endif
@@ -591,7 +606,11 @@ static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb,
#define TAG(x) radeon##x##_RGB565_REV
#define TAG2(x,y) radeon##x##_RGB565_REV##y
#if defined(RADEON_R600)
-#define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off)
+#define GET_VALUE(_x, _y) (LE16_TO_CPU(*(GLushort*)(r600_ptr_color(rrb, _x + x_off, _y + y_off))))
+#define PUT_VALUE(_x, _y, d) { \
+ GLushort *_ptr = (GLushort*)r600_ptr_color( rrb, _x + x_off, _y + y_off ); \
+ *_ptr = CPU_TO_LE16(d); \
+} while (0)
#else
#define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off)
#endif
@@ -605,7 +624,11 @@ static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb,
#define TAG(x) radeon##x##_ARGB1555
#define TAG2(x,y) radeon##x##_ARGB1555##y
#if defined(RADEON_R600)
-#define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off)
+#define GET_VALUE(_x, _y) (LE16_TO_CPU(*(GLushort*)(r600_ptr_color(rrb, _x + x_off, _y + y_off))))
+#define PUT_VALUE(_x, _y, d) { \
+ GLushort *_ptr = (GLushort*)r600_ptr_color( rrb, _x + x_off, _y + y_off ); \
+ *_ptr = CPU_TO_LE16(d); \
+} while (0)
#else
#define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off)
#endif
@@ -617,7 +640,11 @@ static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb,
#define TAG(x) radeon##x##_ARGB1555_REV
#define TAG2(x,y) radeon##x##_ARGB1555_REV##y
#if defined(RADEON_R600)
-#define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off)
+#define GET_VALUE(_x, _y) (LE16_TO_CPU(*(GLushort*)(r600_ptr_color(rrb, _x + x_off, _y + y_off))))
+#define PUT_VALUE(_x, _y, d) { \
+ GLushort *_ptr = (GLushort*)r600_ptr_color( rrb, _x + x_off, _y + y_off ); \
+ *_ptr = CPU_TO_LE16(d); \
+} while (0)
#else
#define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off)
#endif
@@ -631,7 +658,11 @@ static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb,
#define TAG(x) radeon##x##_ARGB4444
#define TAG2(x,y) radeon##x##_ARGB4444##y
#if defined(RADEON_R600)
-#define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off)
+#define GET_VALUE(_x, _y) (LE16_TO_CPU(*(GLushort*)(r600_ptr_color(rrb, _x + x_off, _y + y_off))))
+#define PUT_VALUE(_x, _y, d) { \
+ GLushort *_ptr = (GLushort*)r600_ptr_color( rrb, _x + x_off, _y + y_off ); \
+ *_ptr = CPU_TO_LE16(d); \
+} while (0)
#else
#define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off)
#endif
@@ -643,7 +674,11 @@ static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb,
#define TAG(x) radeon##x##_ARGB4444_REV
#define TAG2(x,y) radeon##x##_ARGB4444_REV##y
#if defined(RADEON_R600)
-#define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off)
+#define GET_VALUE(_x, _y) (LE16_TO_CPU(*(GLushort*)(r600_ptr_color(rrb, _x + x_off, _y + y_off))))
+#define PUT_VALUE(_x, _y, d) { \
+ GLushort *_ptr = (GLushort*)r600_ptr_color( rrb, _x + x_off, _y + y_off ); \
+ *_ptr = CPU_TO_LE16(d); \
+} while (0)
#else
#define GET_PTR(X,Y) radeon_ptr_2byte_8x2(rrb, (X) + x_off, (Y) + y_off)
#endif
@@ -657,10 +692,10 @@ static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb,
#define TAG(x) radeon##x##_xRGB8888
#define TAG2(x,y) radeon##x##_xRGB8888##y
#if defined(RADEON_R600)
-#define GET_VALUE(_x, _y) ((*(GLuint*)(r600_ptr_color(rrb, _x + x_off, _y + y_off)) | 0xff000000))
+#define GET_VALUE(_x, _y) ((LE32_TO_CPU(*(GLuint*)(r600_ptr_color(rrb, _x + x_off, _y + y_off))) | 0xff000000))
#define PUT_VALUE(_x, _y, d) { \
GLuint *_ptr = (GLuint*)r600_ptr_color( rrb, _x + x_off, _y + y_off ); \
- *_ptr = d; \
+ *_ptr = CPU_TO_LE32(d); \
} while (0)
#else
#define GET_VALUE(_x, _y) ((*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off)) | 0xff000000))
@@ -679,10 +714,10 @@ static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb,
#define TAG(x) radeon##x##_ARGB8888
#define TAG2(x,y) radeon##x##_ARGB8888##y
#if defined(RADEON_R600)
-#define GET_VALUE(_x, _y) (*(GLuint*)(r600_ptr_color(rrb, _x + x_off, _y + y_off)))
+#define GET_VALUE(_x, _y) (LE32_TO_CPU(*(GLuint*)(r600_ptr_color(rrb, _x + x_off, _y + y_off))))
#define PUT_VALUE(_x, _y, d) { \
GLuint *_ptr = (GLuint*)r600_ptr_color( rrb, _x + x_off, _y + y_off ); \
- *_ptr = d; \
+ *_ptr = CPU_TO_LE32(d); \
} while (0)
#else
#define GET_VALUE(_x, _y) (*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off)))
@@ -701,10 +736,10 @@ static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb,
#define TAG(x) radeon##x##_BGRx8888
#define TAG2(x,y) radeon##x##_BGRx8888##y
#if defined(RADEON_R600)
-#define GET_VALUE(_x, _y) ((*(GLuint*)(r600_ptr_color(rrb, _x + x_off, _y + y_off)) | 0x000000ff))
+#define GET_VALUE(_x, _y) ((LE32_TO_CPU(*(GLuint*)(r600_ptr_color(rrb, _x + x_off, _y + y_off))) | 0x000000ff))
#define PUT_VALUE(_x, _y, d) { \
GLuint *_ptr = (GLuint*)r600_ptr_color( rrb, _x + x_off, _y + y_off ); \
- *_ptr = d; \
+ *_ptr = CPU_TO_LE32(d); \
} while (0)
#else
#define GET_VALUE(_x, _y) ((*(GLuint*)(radeon_ptr_4byte(rrb, _x + x_off, _y + y_off)) | 0x000000ff))
@@ -723,7 +758,11 @@ static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb,
#define TAG(x) radeon##x##_BGRA8888
#define TAG2(x,y) radeon##x##_BGRA8888##y
#if defined(RADEON_R600)
-#define GET_PTR(X,Y) r600_ptr_color(rrb, (X) + x_off, (Y) + y_off)
+#define GET_VALUE(_x, _y) (LE32_TO_CPU(*(GLuint*)(r600_ptr_color(rrb, _x + x_off, _y + y_off))))
+#define PUT_VALUE(_x, _y, d) { \
+ GLuint *_ptr = (GLuint*)r600_ptr_color( rrb, _x + x_off, _y + y_off ); \
+ *_ptr = CPU_TO_LE32(d); \
+} while (0)
#else
#define GET_PTR(X,Y) radeon_ptr_4byte(rrb, (X) + x_off, (Y) + y_off)
#endif
@@ -752,7 +791,7 @@ static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb,
*(GLushort *)r200_depth_2byte(rrb, _x + x_off, _y + y_off) = d
#elif defined(RADEON_R600)
#define WRITE_DEPTH( _x, _y, d ) \
- *(GLushort *)r600_ptr_depth(rrb, _x + x_off, _y + y_off) = d
+ *(GLushort *)r600_ptr_depth(rrb, _x + x_off, _y + y_off) = CPU_TO_LE16(d)
#else
#define WRITE_DEPTH( _x, _y, d ) \
*(GLushort *)radeon_ptr_2byte_8x2(rrb, _x + x_off, _y + y_off) = d
@@ -763,7 +802,7 @@ static GLubyte *radeon_ptr_2byte_8x2(const struct radeon_renderbuffer * rrb,
d = *(GLushort *)r200_depth_2byte(rrb, _x + x_off, _y + y_off)
#elif defined(RADEON_R600)
#define READ_DEPTH( d, _x, _y ) \
- d = *(GLushort *)r600_ptr_depth(rrb, _x + x_off, _y + y_off)
+ d = LE16_TO_CPU(*(GLushort *)r600_ptr_depth(rrb, _x + x_off, _y + y_off))
#else
#define READ_DEPTH( d, _x, _y ) \
d = *(GLushort *)radeon_ptr_2byte_8x2(rrb, _x + x_off, _y + y_off)
@@ -792,10 +831,10 @@ do { \
#define WRITE_DEPTH( _x, _y, d ) \
do { \
GLuint *_ptr = (GLuint*)r600_ptr_depth( rrb, _x + x_off, _y + y_off ); \
- GLuint tmp = *_ptr; \
+ GLuint tmp = LE32_TO_CPU(*_ptr); \
tmp &= 0xff000000; \
tmp |= ((d) & 0x00ffffff); \
- *_ptr = tmp; \
+ *_ptr = CPU_TO_LE32(tmp); \
} while (0)
#elif defined(RADEON_R200)
#define WRITE_DEPTH( _x, _y, d ) \
@@ -825,7 +864,7 @@ do { \
#elif defined(RADEON_R600)
#define READ_DEPTH( d, _x, _y ) \
do { \
- d = (*(GLuint*)(r600_ptr_depth(rrb, _x + x_off, _y + y_off)) & 0x00ffffff); \
+ d = (LE32_TO_CPU(*(GLuint*)(r600_ptr_depth(rrb, _x + x_off, _y + y_off))) & 0x00ffffff); \
}while(0)
#elif defined(RADEON_R200)
#define READ_DEPTH( d, _x, _y ) \
@@ -858,15 +897,15 @@ do { \
#define WRITE_DEPTH( _x, _y, d ) \
do { \
GLuint *_ptr = (GLuint*)r600_ptr_depth( rrb, _x + x_off, _y + y_off ); \
- GLuint tmp = *_ptr; \
+ GLuint tmp = LE32_TO_CPU(*_ptr); \
tmp &= 0xff000000; \
tmp |= ((d) & 0x00ffffff); \
- *_ptr = tmp; \
+ *_ptr = CPU_TO_LE32(tmp); \
_ptr = (GLuint*)r600_ptr_stencil(rrb, _x + x_off, _y + y_off); \
- tmp = *_ptr; \
+ tmp = LE32_TO_CPU(*_ptr); \
tmp &= 0xffffff00; \
tmp |= ((d) >> 24) & 0xff; \
- *_ptr = tmp; \
+ *_ptr = CPU_TO_LE32(tmp); \
} while (0)
#elif defined(RADEON_R200)
#define WRITE_DEPTH( _x, _y, d ) \
@@ -891,8 +930,8 @@ do { \
#elif defined(RADEON_R600)
#define READ_DEPTH( d, _x, _y ) \
do { \
- d = (*(GLuint*)(r600_ptr_depth(rrb, _x + x_off, _y + y_off))) & 0x00ffffff; \
- d |= ((*(GLuint*)(r600_ptr_stencil(rrb, _x + x_off, _y + y_off))) << 24) & 0xff000000; \
+ d = (LE32_TO_CPU(*(GLuint*)(r600_ptr_depth(rrb, _x + x_off, _y + y_off))) & 0x00ffffff); \
+ d |= ((LE32_TO_CPU(*(GLuint*)(r600_ptr_stencil(rrb, _x + x_off, _y + y_off))) << 24) & 0xff000000); \
}while(0)
#elif defined(RADEON_R200)
#define READ_DEPTH( d, _x, _y ) \
@@ -927,10 +966,10 @@ do { \
#define WRITE_STENCIL( _x, _y, d ) \
do { \
GLuint *_ptr = (GLuint*)r600_ptr_stencil(rrb, _x + x_off, _y + y_off); \
- GLuint tmp = *_ptr; \
+ GLuint tmp = LE32_TO_CPU(*_ptr); \
tmp &= 0xffffff00; \
tmp |= (d) & 0xff; \
- *_ptr = tmp; \
+ *_ptr = CPU_TO_LE32(tmp); \
} while (0)
#elif defined(RADEON_R200)
#define WRITE_STENCIL( _x, _y, d ) \
@@ -963,7 +1002,7 @@ do { \
#define READ_STENCIL( d, _x, _y ) \
do { \
GLuint *_ptr = (GLuint*)r600_ptr_stencil( rrb, _x + x_off, _y + y_off ); \
- GLuint tmp = *_ptr; \
+ GLuint tmp = LE32_TO_CPU(*_ptr); \
d = tmp & 0x000000ff; \
} while (0)
#elif defined(RADEON_R200)