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-rw-r--r--src/intel/vulkan/genX_pipeline.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 078b3f2b462..5594726e4a2 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -999,6 +999,7 @@ emit_ds_state(struct anv_pipeline *pipeline,
pipeline->stencil_test_enable = false;
pipeline->writes_depth = false;
pipeline->depth_test_enable = false;
+ pipeline->depth_bounds_test_enable = false;
memset(depth_stencil_dw, 0, sizeof(depth_stencil_dw));
return;
}
@@ -1017,8 +1018,6 @@ emit_ds_state(struct anv_pipeline *pipeline,
pipeline->depth_test_enable = info.depthTestEnable;
pipeline->depth_bounds_test_enable = info.depthBoundsTestEnable;
- /* VkBool32 depthBoundsTestEnable; // optional (depth_bounds_test) */
-
#if GEN_GEN <= 7
struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
#else