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-rw-r--r--.pick_status.json16391
-rw-r--r--VERSION2
-rw-r--r--docs/conf.py2
-rw-r--r--docs/relnotes/22.1.2.rst2
-rw-r--r--docs/relnotes/22.1.3.rst208
-rw-r--r--docs/relnotes/22.1.4.rst107
-rw-r--r--docs/relnotes/22.1.5.rst159
-rw-r--r--docs/relnotes/22.1.6.rst0
-rw-r--r--src/amd/common/ac_nir_lower_ngg.c17
-rw-r--r--src/amd/compiler/aco_insert_exec_mask.cpp3
-rw-r--r--src/amd/compiler/aco_optimizer.cpp10
-rw-r--r--src/amd/compiler/aco_register_allocation.cpp1
-rw-r--r--src/amd/compiler/aco_validate.cpp5
-rw-r--r--src/amd/llvm/ac_llvm_build.c33
-rw-r--r--src/amd/vulkan/radv_cmd_buffer.c17
-rw-r--r--src/amd/vulkan/radv_pipeline_rt.c8
-rw-r--r--src/amd/vulkan/radv_query.c7
-rw-r--r--src/amd/vulkan/radv_shader_info.c4
-rw-r--r--src/broadcom/ci/broadcom-rpi3-fails.txt151
-rw-r--r--src/broadcom/ci/broadcom-rpi3-flakes.txt2
-rw-r--r--src/broadcom/ci/broadcom-rpi3-skips.txt2
-rw-r--r--src/broadcom/compiler/vir_register_allocate.c27
-rw-r--r--src/broadcom/vulkan/v3dv_descriptor_set.c2
-rw-r--r--src/broadcom/vulkan/v3dv_device.c4
-rw-r--r--src/broadcom/vulkan/v3dv_uniforms.c13
-rw-r--r--src/compiler/nir/nir.h2
-rw-r--r--src/compiler/nir/nir_deref.c277
-rw-r--r--src/compiler/nir/nir_lower_point_size_mov.c17
-rw-r--r--src/compiler/nir/nir_opcodes.py12
-rw-r--r--src/compiler/nir/nir_opt_algebraic.py8
-rw-r--r--src/compiler/nir/nir_opt_shrink_vectors.c6
-rw-r--r--src/compiler/nir/nir_serialize.c12
-rw-r--r--src/compiler/nir/tests/vars_tests.cpp384
-rw-r--r--src/compiler/nir_types.cpp2
-rw-r--r--src/compiler/spirv/spirv_to_nir.c3
-rw-r--r--src/egl/drivers/dri2/platform_wayland.c5
-rw-r--r--src/egl/drivers/dri2/platform_x11.c28
-rw-r--r--src/freedreno/ci/freedreno-a630-fails.txt24
-rw-r--r--src/freedreno/vulkan/tu_clear_blit.c37
-rw-r--r--src/freedreno/vulkan/tu_pipeline.c4
-rw-r--r--src/freedreno/vulkan/tu_util.h6
-rw-r--r--src/gallium/auxiliary/gallivm/lp_bld_limits.h2
-rw-r--r--src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c3
-rw-r--r--src/gallium/auxiliary/nir/tgsi_to_nir.c3
-rw-r--r--src/gallium/auxiliary/pipe-loader/driinfo_gallium.h1
-rw-r--r--src/gallium/auxiliary/util/u_blitter.c7
-rw-r--r--src/gallium/auxiliary/util/u_driconf.c1
-rw-r--r--src/gallium/auxiliary/util/u_threaded_context.c19
-rw-r--r--src/gallium/auxiliary/util/u_threaded_context_calls.h1
-rw-r--r--src/gallium/drivers/crocus/crocus_fence.c2
-rw-r--r--src/gallium/drivers/crocus/crocus_query.c3
-rw-r--r--src/gallium/drivers/crocus/crocus_state.c4
-rw-r--r--src/gallium/drivers/d3d12/d3d12_nir_passes.c1
-rw-r--r--src/gallium/drivers/iris/iris_fence.c2
-rw-r--r--src/gallium/drivers/iris/iris_state.c83
-rw-r--r--src/gallium/drivers/lima/ci/lima-fails.txt10
-rw-r--r--src/gallium/drivers/lima/lima_context.c2
-rw-r--r--src/gallium/drivers/llvmpipe/lp_context.c12
-rw-r--r--src/gallium/drivers/llvmpipe/lp_context.h2
-rw-r--r--src/gallium/drivers/llvmpipe/lp_flush.c22
-rw-r--r--src/gallium/drivers/llvmpipe/lp_linear_sampler.c12
-rw-r--r--src/gallium/drivers/llvmpipe/lp_rast.c14
-rw-r--r--src/gallium/drivers/llvmpipe/lp_rast.h3
-rw-r--r--src/gallium/drivers/llvmpipe/lp_rast_priv.h2
-rw-r--r--src/gallium/drivers/llvmpipe/lp_screen.c2
-rw-r--r--src/gallium/drivers/llvmpipe/lp_screen.h4
-rw-r--r--src/gallium/drivers/llvmpipe/lp_setup.c26
-rw-r--r--src/gallium/drivers/llvmpipe/lp_setup.h1
-rw-r--r--src/gallium/drivers/llvmpipe/lp_setup_context.h1
-rw-r--r--src/gallium/drivers/llvmpipe/lp_state_fs.c2
-rw-r--r--src/gallium/drivers/llvmpipe/lp_state_fs_analysis.c6
-rw-r--r--src/gallium/drivers/panfrost/pan_blit.c10
-rw-r--r--src/gallium/drivers/panfrost/pan_cmdstream.c10
-rw-r--r--src/gallium/drivers/panfrost/pan_context.c28
-rw-r--r--src/gallium/drivers/panfrost/pan_job.c25
-rw-r--r--src/gallium/drivers/panfrost/pan_resource.h3
-rw-r--r--src/gallium/drivers/r300/compiler/radeon_optimize.c3
-rw-r--r--src/gallium/drivers/r300/compiler/radeon_rename_regs.c4
-rw-r--r--src/gallium/drivers/radeonsi/si_compute.c2
-rw-r--r--src/gallium/drivers/radeonsi/si_fence.c2
-rw-r--r--src/gallium/drivers/radeonsi/si_pipe.h22
-rw-r--r--src/gallium/drivers/radeonsi/si_state_draw.cpp17
-rw-r--r--src/gallium/drivers/radeonsi/si_state_shaders.cpp2
-rw-r--r--src/gallium/drivers/vc4/vc4_nir_lower_txf_ms.c1
-rw-r--r--src/gallium/drivers/virgl/virgl_tgsi.c2
-rw-r--r--src/gallium/drivers/zink/ci/zink-lvp-fails.txt2
-rw-r--r--src/gallium/drivers/zink/ci/zink-radv-fails.txt2
-rw-r--r--src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c21
-rw-r--r--src/gallium/drivers/zink/nir_to_spirv/spirv_builder.c12
-rw-r--r--src/gallium/drivers/zink/nir_to_spirv/spirv_builder.h4
-rw-r--r--src/gallium/drivers/zink/zink_blit.c5
-rw-r--r--src/gallium/drivers/zink/zink_bo.c8
-rw-r--r--src/gallium/drivers/zink/zink_clear.c10
-rw-r--r--src/gallium/drivers/zink/zink_compiler.c6
-rw-r--r--src/gallium/drivers/zink/zink_compiler.h6
-rw-r--r--src/gallium/drivers/zink/zink_context.c40
-rw-r--r--src/gallium/drivers/zink/zink_context.h6
-rw-r--r--src/gallium/drivers/zink/zink_descriptors_lazy.c3
-rw-r--r--src/gallium/drivers/zink/zink_draw.cpp109
-rw-r--r--src/gallium/drivers/zink/zink_fence.c7
-rw-r--r--src/gallium/drivers/zink/zink_framebuffer.c25
-rw-r--r--src/gallium/drivers/zink/zink_framebuffer.h4
-rw-r--r--src/gallium/drivers/zink/zink_kopper.c2
-rw-r--r--src/gallium/drivers/zink/zink_program.c25
-rw-r--r--src/gallium/drivers/zink/zink_query.c2
-rw-r--r--src/gallium/drivers/zink/zink_resource.c38
-rw-r--r--src/gallium/drivers/zink/zink_resource.h2
-rw-r--r--src/gallium/drivers/zink/zink_screen.c7
-rw-r--r--src/gallium/drivers/zink/zink_screen.h1
-rw-r--r--src/gallium/drivers/zink/zink_state.c2
-rw-r--r--src/gallium/frontends/lavapipe/lvp_device.c8
-rw-r--r--src/gallium/frontends/lavapipe/lvp_execute.c10
-rw-r--r--src/gallium/frontends/lavapipe/lvp_formats.c7
-rw-r--r--src/gallium/frontends/lavapipe/lvp_pipeline.c86
-rw-r--r--src/gallium/frontends/nine/nine_memory_helper.c2
-rw-r--r--src/gallium/include/frontend/api.h1
-rw-r--r--src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c20
-rw-r--r--src/glx/drisw_glx.c14
-rw-r--r--src/glx/drisw_priv.h1
-rw-r--r--src/intel/blorp/blorp_genX_exec.h4
-rw-r--r--src/intel/common/intel_clflush.h3
-rw-r--r--src/intel/common/intel_urb_config.c5
-rw-r--r--src/intel/compiler/brw_compiler.h9
-rw-r--r--src/intel/compiler/brw_fs.cpp14
-rw-r--r--src/intel/compiler/brw_fs_generator.cpp2
-rw-r--r--src/intel/compiler/brw_fs_nir.cpp13
-rw-r--r--src/intel/compiler/brw_mesh.cpp29
-rw-r--r--src/intel/dev/intel_hwconfig.c4
-rw-r--r--src/intel/isl/isl.h3
-rw-r--r--src/intel/isl/isl_format.c29
-rw-r--r--src/intel/vulkan/anv_cmd_buffer.c3
-rw-r--r--src/intel/vulkan/anv_descriptor_set.c9
-rw-r--r--src/intel/vulkan/anv_device.c52
-rw-r--r--src/intel/vulkan/anv_image.c109
-rw-r--r--src/intel/vulkan/anv_pipeline.c53
-rw-r--r--src/intel/vulkan/anv_private.h26
-rw-r--r--src/intel/vulkan/genX_blorp_exec.c2
-rw-r--r--src/intel/vulkan/genX_cmd_buffer.c135
-rw-r--r--src/intel/vulkan/genX_pipeline.c5
-rw-r--r--src/intel/vulkan/gfx7_cmd_buffer.c3
-rw-r--r--src/mesa/main/bufferobj.c3
-rw-r--r--src/mesa/main/consts_exts.h3
-rw-r--r--src/mesa/main/externalobjects.c2
-rw-r--r--src/mesa/state_tracker/st_extensions.c2
-rw-r--r--src/panfrost/bifrost/ISA.xml2
-rw-r--r--src/panfrost/lib/meson.build1
-rw-r--r--src/panfrost/lib/pan_earlyzs.c119
-rw-r--r--src/panfrost/lib/pan_earlyzs.h80
-rw-r--r--src/util/00-mesa-defaults.conf2
-rw-r--r--src/util/bitset.h7
-rw-r--r--src/util/driconf.h3
-rw-r--r--src/util/u_atomic.h6
-rw-r--r--src/virtio/vulkan/vn_buffer.c4
-rw-r--r--src/virtio/vulkan/vn_device.c20
-rw-r--r--src/vulkan/runtime/vk_nir.c15
-rw-r--r--src/vulkan/wsi/wsi_common.c11
-rw-r--r--src/vulkan/wsi/wsi_common_wayland.c2
-rw-r--r--src/vulkan/wsi/wsi_common_x11.c85
158 files changed, 18753 insertions, 1012 deletions
diff --git a/.pick_status.json b/.pick_status.json
index 903e77e8b31..2dec29fd3e7 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -1,5 +1,16376 @@
[
{
+ "sha": "9b844d7c42129925525d613c19622b11aee16298",
+ "description": "tu: Add debug option to use emulated renderpass support",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "b90d628a7dbf0b053f1de51d6455f2a7e294b05f",
+ "description": "tu: Use common vk_image_view base struct",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "89263fde2057b91fa3c8a507bde1e03c661b0054",
+ "description": "tu: Use common vk_image struct",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "cb0f414b2aed88f48b2593dad833844be2f5f42b",
+ "description": "tu: Add support for suspending and resuming renderpasses",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "0a4c86fc44a64eba9f35820e9b7e5b0a651a081f",
+ "description": "util/trace: Fix u_trace_*_iterator with no tracepoints",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "3aa20a4409eedce70acc282cec12f5af12498b33",
+ "description": "tu: Split out some state into a separate struct",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "9689433eee8c1ce397ec49c53d8f7fbafa7940e8",
+ "description": "tu: Update more state with secondaries",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "79c7c6e492370e9a63813562c963f7b2d32ad235",
+ "description": "tu: Remove has_subpass_predication",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "ed125e6cca188275631641784fcf3ddcbcfef193",
+ "description": "tu: Initial support for dynamic rendering",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "22be08a21e9ec7dbe5d6d0be8cbce931d064a554",
+ "description": "tu: Remove usage of RenderPassBeginInfo",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "cf391db4c6d727320608d8ea28343d9dd35dde85",
+ "description": "tu: Move tu_render_pass definition up",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "2b8b5259c712bad47f3ceddd567ced68ba07ed9d",
+ "description": "tu: Disable GMEM for multiview inside tu_render_pass_gmem_config",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "c42e7aa46cde839d7ecba1737505f40a076efb83",
+ "description": "tu: Move TU_DONT_CARE_AS_LOAD into attachment_set_ops()",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "907b892bb20de2af07483f9699fe2cf4535c6078",
+ "description": "tu: Rewrite tess factor emission",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "c5be4445004e4980a1897b904fc206b3d030c58f",
+ "description": "tu: Treat CP_WAIT_FOR_ME as a cache invalidate",
+ "nominated": true,
+ "nomination_type": 1,
+ "resolution": 0,
+ "main_sha": null,
+ "because_sha": "37939e9c5462b871b0b9b00a43c5c9bec1e10e9d"
+ },
+ {
+ "sha": "d2ad4c739c09767c23c8a2b598733c93f2ace9a6",
+ "description": "tu/lrz: Do not use framebuffer when inheriting LRZ",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "df4b5914cd5dd64cbf9099c4b8388acf2ac75750",
+ "description": "nir/fold_16bit_tex_image: Default to only_fold_all.",
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+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "dd3e9be413ad1c5a2c834451af7af0acccae4241",
+ "description": "radeonsi: Stop using nir_legalize_16bit_sampler_srcs.",
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+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "365466a10c88806734fd96378541c9a62579f739",
+ "description": "zink/turnip: Add comments to already triaged failures for tu baseline",
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+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "8001c78d49580b89eac970c4201ab2561473ffbb",
+ "description": "ir3: set UL flag before ir3_lower_subgroups",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "7023cab0935c4286ab6dc011e22fe76e4a47f85a",
+ "description": "llvmpipe: fix texcoord analysis regression",
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+ "nomination_type": 1,
+ "resolution": 0,
+ "main_sha": null,
+ "because_sha": "90d011de8ee16e954a4da0dde8c072cbbf3bafcc"
+ },
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+ "description": "aco/ir: Add swapped opcode for v_cmp_u/v_cmp_o.",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
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+ "description": "aco/ir: Add v_cmp_class to get_cmp_info.",
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+ "resolution": 4,
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+ "because_sha": null
+ },
+ {
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+ "description": "aco/ir: Add vcmpx opcode to get_cmp_info.",
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+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
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+ "description": "aco/ir: Fix swapped nle.",
+ "nominated": true,
+ "nomination_type": 0,
+ "resolution": 0,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "9c727b958e22f4e25a05b647fa6a56a65af72e59",
+ "description": "aco/ir: Add integer get_cmp_info.",
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+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "590b93ae65d159b6fd3ad83f2637ce6e5d429d3e",
+ "description": "aco/ir: Generalize (un)ordered_swapped.",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "f286cab27bfa1367f8c82c4db6d2d0a6df860e0f",
+ "description": "pvr: Move BRN 44079, 48492 and 66011 code into pvrsrvkm specific directory",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "fa79020ba982d99d9c68ad63f1979ad21afbff10",
+ "description": "anv: Fix PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES with large BAR",
+ "nominated": false,
+ "nomination_type": 1,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": "fae88d8791b2903771c85958903ee81080b66aec"
+ },
+ {
+ "sha": "11e51f7211f7d26cb679605cecc18a7a85f74e8d",
+ "description": "radv: Use NIR-based NGG lowering with LLVM.",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "45ed22c87ee7f1b044f7bdbab54cfcd4f7eba678",
+ "description": "radv: Properly set LDS size for LLVM NGG shaders.",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "d3dcd294c09880d574ed2efbbb1c251f7c7f0fa9",
+ "description": "radv/llvm: Remove incorrect hardcoded workgroup size from NGG GS.",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "7e7d6d8c73871671a3c6f4ada17e83597b6272f2",
+ "description": "ac/llvm: Implement GDS atomic add NIR intrinsic.",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "19f62b430369760ccfa246da6fcd3686e495f2df",
+ "description": "dri: add [ax]bgr16161616 to format lookup tables",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "7e554e11a1795d3db8f22b7ed059735f06ee4ca8",
+ "description": "dri: fix incorrect fourcc for R16G16B16A16_UNORM format",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
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+ "sha": "c9b2c79d16d0e7d79712483bf979a8eff2b42ea9",
+ "description": "d3d12: Keep access masks up-to-date when removing vars in d3d12_disable_multisampling()",
+ "nominated": true,
+ "nomination_type": 1,
+ "resolution": 1,
+ "main_sha": null,
+ "because_sha": "e5cf19fced6feff07bcd6b288f6370feb21a496f"
+ },
+ {
+ "sha": "e1accb1c4c505b4b32b5141d89865181a47567dc",
+ "description": "util: Fix invalid usage of alignas in u_cpu_detect.c",
+ "nominated": false,
+ "nomination_type": 1,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": "e3bc78b8e398348bc1993b1c713b8917bd4d53d9"
+ },
+ {
+ "sha": "e24354c1b2e0e2dc23b6acf227f26a55fbf3fabd",
+ "description": "radeonsi/gfx11: rework GDS streamout code to single-lane and enable streamout",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "44e4d42c23891b0cb16949fe7100555df170bab7",
+ "description": "radeonsi/gfx11: add missing register shadowing code",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "fbd68a3839b84f53bd4451163abca5463d5dbd5f",
+ "description": "radeonsi/gfx11: drop the ES vertex count requirement",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "99fd408946ed6097f1cb40fcc44d4d66a7896b41",
+ "description": "radeonsi/gfx11: don't allocate unused wait_mem_scratch",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "98d6a3d6c6fbd15d3e7affb7c1bce825ce298b0a",
+ "description": "radeonsi/gfx11: don't use memory for waiting for cache flushes",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "56d4e0be86b50c5f6bddeef22c92332b8549d833",
+ "description": "radeonsi/gfx11: synchronize correctly before setting SPI_ATTRIBUTE_RING_*",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "fa25eba744b84876bd7ebc72ace5e86052cda1bf",
+ "description": "radeonsi/gfx11: allocate more space for pipeline statistics",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "0e8beb1eed994cc951bf53d90dd4664d2a5b5a28",
+ "description": "radeonsi/gfx11: compile monolithic PS if it writes memory",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "ee7150da79b9b8f6bddf179cdb032bfe9877b8ff",
+ "description": "amd/gfx11: add PixelWaitSync packet fields",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "7d8847d963bec141fd45d0d6c08e608a3fa34b69",
+ "description": "ac/llvm: fix tcs_wave_id unpacking on gfx11",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "ae432b67b780e7cd7c99f24eecf4f01657a6a8b0",
+ "description": "ci/dzn: Skip a test that intermittently times out at a minute.",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "15f394cc7a2e47c487c7fe7c45e0fc55baa71ddc",
+ "description": "nir: Fix unused-variable compile warnings",
+ "nominated": true,
+ "nomination_type": 1,
+ "resolution": 1,
+ "main_sha": null,
+ "because_sha": "8492e78f9d14c187596c13725f6974816d02a0e9"
+ },
+ {
+ "sha": "75973e3a1cd082bf3575139f19f4921b7705485a",
+ "description": "ci/lava: Add support for more complex color codes",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "08435b1c6f9062ba4cd4e56803dd9e19ea119b3a",
+ "description": "radv: Always use 3D block ID and grid size in task shaders.",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "0fb9573c57f50b064e8a4fb148ef3845313de072",
+ "description": "ac/nir/taskmesh: Preserve workgroup ID Y and Z when applying firstTask.",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "b243e94f07fc63523c3ed8163b8c3ce3965c0c82",
+ "description": "radv: Lower mesh shader 3D workgroup ID to 1D index.",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "e05f63f56c1563b6ac85e5158f90040572c229ad",
+ "description": "ac/nir/ngg: Add mesh shader workgroup index.",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "856a8acab09d5e4f4c8a0f0073ef7dbda663d0f2",
+ "description": "radv: Enable NGG wave ID for mesh shader scratch ring.",
+ "nominated": false,
+ "nomination_type": 1,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": "0280b526d58e85d65b53d3f9c8b0f7364d853751"
+ },
+ {
+ "sha": "a9e2c699aa3677e24a58de10c5e68ecb950f4a94",
+ "description": "util/c11: Update function u_thread_create to be c11 conformance",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "6e33ef2bb9d096bdac40678e5cf5dda3e98fef7b",
+ "description": "c11: Implement thread_local in c11/threads.h",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "09cd5c9bdb8c3c48fadcef6c92da2b67acbfcb47",
+ "description": "c11: Fixes memory leak of pack in thrd_create on win32",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "e6392fcf3d8b8dd7e3a8427755d8be2f2332366a",
+ "description": "c11: Move the implementation of threads.h into c source code",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "b7773fd105af14d3c8b561df922adc2eda599d10",
+ "description": "util: Define WIN32_LEAN_AND_MEAN before include of `windows.h` in u_thread.h",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "be00a7c8acf04d9efde831efe251a59c71b725e7",
+ "description": "glx: using C++11 keyword thread_local",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "0f3064ee445c395fdb09428c48c7ed42b5b7b486",
+ "description": "intel: using C++11 keyword thread_local",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
+ "sha": "af0080c4ef6df7466a20007fc94b59489d931f4d",
+ "description": "turnip: advertise VK_EXT_border_color_swizzle",
+ "nominated": false,
+ "nomination_type": null,
+ "resolution": 4,
+ "main_sha": null,
+ "because_sha": null
+ },
+ {
"sha": "ea33e44ce4f95ce45729b75dee34be50df749f09",
"description": "ci/crosvm: clean crosvm socket",
"nominated": false,
@@ -13,7 +16384,7 @@
"description": "zink/ci: update list of failures again",
"nominated": true,
"nomination_type": 1,
- "resolution": 0,
+ "resolution": 2,
"main_sha": null,
"because_sha": "b240be28e3193e83632848bb32eb1013bddfc285"
},
@@ -3352,7 +19723,7 @@
"description": "nir/deref: Handle RESTRICT for SSBO deref bindings",
"nominated": true,
"nomination_type": 0,
- "resolution": 0,
+ "resolution": 1,
"main_sha": null,
"because_sha": null
},
@@ -3361,7 +19732,7 @@
"description": "nir/deref: Handle SSBO array bindings specially",
"nominated": true,
"nomination_type": 0,
- "resolution": 0,
+ "resolution": 1,
"main_sha": null,
"because_sha": null
},
@@ -3370,7 +19741,7 @@
"description": "nir/vars_tests: Use nir_var_mem_global instead of ssbo",
"nominated": true,
"nomination_type": 0,
- "resolution": 0,
+ "resolution": 1,
"main_sha": null,
"because_sha": null
},
@@ -3379,7 +19750,7 @@
"description": "nir: Increase nir_variable_data::mode to 16 bits",
"nominated": true,
"nomination_type": 0,
- "resolution": 0,
+ "resolution": 1,
"main_sha": null,
"because_sha": null
},
@@ -3388,7 +19759,7 @@
"description": "nir/deref: Re-arrange variable checks in compare_deref_paths",
"nominated": true,
"nomination_type": 0,
- "resolution": 0,
+ "resolution": 1,
"main_sha": null,
"because_sha": null
},
@@ -3397,7 +19768,7 @@
"description": "nir/deref: Make compare_deref_paths take a stop callback",
"nominated": true,
"nomination_type": 0,
- "resolution": 0,
+ "resolution": 1,
"main_sha": null,
"because_sha": null
},
@@ -3406,7 +19777,7 @@
"description": "nir/deref: Use an index in compare_deref_paths",
"nominated": true,
"nomination_type": 0,
- "resolution": 0,
+ "resolution": 1,
"main_sha": null,
"because_sha": null
},
@@ -3415,7 +19786,7 @@
"description": "nir/deref: Break out a helper for compare_deref_paths",
"nominated": true,
"nomination_type": 0,
- "resolution": 0,
+ "resolution": 1,
"main_sha": null,
"because_sha": null
},
@@ -3424,7 +19795,7 @@
"description": "nir/deref: stop assuming coherent accesses of different SSBOs may alias",
"nominated": true,
"nomination_type": 0,
- "resolution": 0,
+ "resolution": 1,
"main_sha": null,
"because_sha": null
},
diff --git a/VERSION b/VERSION
index 30ed8778377..08a1fa9757e 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-22.1.2
+22.1.6 \ No newline at end of file
diff --git a/docs/conf.py b/docs/conf.py
index ab4c3380ef0..96399515576 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -74,7 +74,7 @@ release = 'latest'
#
# This is also used if you do content translation via gettext catalogs.
# Usually you set "language" from the command line for these cases.
-language = None
+language = 'en'
# List of patterns, relative to source directory, that match files and
# directories to ignore when looking for source files.
diff --git a/docs/relnotes/22.1.2.rst b/docs/relnotes/22.1.2.rst
index 6157c411b4e..b403181b89c 100644
--- a/docs/relnotes/22.1.2.rst
+++ b/docs/relnotes/22.1.2.rst
@@ -19,7 +19,7 @@ SHA256 checksum
::
- TBD.
+ 0971226b4a6a3d10cfc255736b33e4017e18c14c9db1e53863ac1f8ae0deb9ea mesa-22.1.2.tar.xz
New features
diff --git a/docs/relnotes/22.1.3.rst b/docs/relnotes/22.1.3.rst
new file mode 100644
index 00000000000..4a9d2b0aedd
--- /dev/null
+++ b/docs/relnotes/22.1.3.rst
@@ -0,0 +1,208 @@
+Mesa 22.1.3 Release Notes / 2022-06-29
+======================================
+
+Mesa 22.1.3 is a bug fix release which fixes bugs found since the 22.1.2 release.
+
+Mesa 22.1.3 implements the OpenGL 4.6 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.6. OpenGL
+4.6 is **only** available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+
+Mesa 22.1.3 implements the Vulkan 1.2 API, but the version reported by
+the apiVersion property of the VkPhysicalDeviceProperties struct
+depends on the particular driver being used.
+
+SHA256 checksum
+---------------
+
+::
+
+ b98f32ba7aa2a1ff5725fb36eb999c693079f0ca16f70aa2f103e2b6c3f093e3 mesa-22.1.3.tar.xz
+
+
+New features
+------------
+
+- None
+
+
+Bug fixes
+---------
+
+- [Crocus] - Minecraft with Forge and JourneyMap - Graphical glitches
+- intel - Minecraft char bar is broken after Mesa upgrade
+- [wine] RAGE: texture problems
+- "Unsupported modifier, resource creation failed." on stderr
+- anv: query regressions
+- ci: docs build fail
+
+
+Changes
+-------
+
+Alyssa Rosenzweig (2):
+
+- pan/bi: Fix LD_BUFFER.i16 definition
+- lima,panfrost: Do not ralloc contexts against the screen
+
+Boris Brezillon (3):
+
+- d3d12: Keep access masks up-to-date when removing vars in d3d12_disable_multisampling()
+- nir/serialize: Put dest last in packed_instr::tex
+- nir/serialize: Support texop >= 16
+
+Christian Gmeiner (1):
+
+- nir: Fix unused-variable compile warnings
+
+Connor Abbott (4):
+
+- tu: Fix 3d GMEM store swizzle in texture descriptor
+- tu: Add missing WFI to the 3d GMEM store path
+- tu: Save/restore \*_BIN_CONTROL in 3d GMEM store path
+- tu: Fix linemode for tessellation with isolines
+
+Dave Airlie (4):
+
+- llvmpipe: disable alpha test branch if multisample is enabled.
+- egl/x11: split large put image requests to avoid server destroy
+- egl/x11: add missing put_image cookie cleanups
+- wsi/x11: add xcb_put_image support for larger transfers.
+
+Dylan Baker (9):
+
+- docs: add sha256sum to 22.1.2 notes
+- .pick_status.json: Update to 09a7304d5abf5b847cf5feb2d97758bee1696566
+- .pick_status.json: Update to 2866ae32da0348caf71ad2d11c353321df626ff4
+- .pick_status.json: Update to 8ce7faab47a77377a6a1313a80580828b052f878
+- .pick_status.json: Mark 420270cb4f73da6251d4caec976358681f05c45c as backported
+- .pick_status.json: Update to 9527fbe596e2ace276c158f67a900c29aad6cdd0
+- .pick_status.json: Update to 9d7d1c0637529301d3e319ec5f1c883c5f249783
+- lima/ci: mark some tests as pass
+- .pick_status.json: Update to 58313f3257b338928a8ae4ea375eedb50accf2bb
+
+Emma Anholt (1):
+
+- vc4: Propagate txf_ms's dest_type to the lowered txf.
+
+Erik Faye-Lund (1):
+
+- docs: set language to english
+
+Filip Gawin (1):
+
+- r300: prefer old not native swizzle in constant folding
+
+Iago Toral Quiroga (3):
+
+- v3dv: fix leak
+- broadcom/compiler: fix postponed TMU spills with multiple writes
+- broadcom/compiler: don't predicate postponed spills
+
+Ian Romanick (3):
+
+- intel/fs: Add missing synchronization for WaW dependency
+- nir: i32csel opcodes should compare with integer zero
+- nir/algebraic: Fix NaN-unsafe fcsel patterns
+
+Icecream95 (1):
+
+- panfrost: Remove sync arguments from panfrost_batch_submit
+
+Italo Nicola (1):
+
+- virgl: overpropagate precise flags
+
+Iván Briano (1):
+
+- anv: do not get rid of empty/useless fragment shaders
+
+Jason Ekstrand (9):
+
+- nir/deref: Break out a helper for compare_deref_paths
+- nir/deref: Use an index in compare_deref_paths
+- nir/deref: Make compare_deref_paths take a stop callback
+- nir/deref: Re-arrange variable checks in compare_deref_paths
+- nir: Increase nir_variable_data::mode to 16 bits
+- nir/vars_tests: Use nir_var_mem_global instead of ssbo
+- nir/deref: Handle SSBO array bindings specially
+- nir/deref: Handle RESTRICT for SSBO deref bindings
+- anv: Properly clamp attachment layer counts
+
+Lionel Landwerlin (2):
+
+- vulkan/wsi: fix crash with debug names on swapchain
+- anv: limit RT writes to number of color outputs
+
+Marcin Ślusarz (2):
+
+- intel/common: allocate space for at least one task urb
+- intel/compiler: adjust task payload offsets as late as possible
+
+Mike Blumenkrantz (27):
+
+- zink: rename a variable
+- zink: unify actual map calls in buffer mapping
+- zink: use only the extents for buffer unmap flushes
+- zink: fix buffer transfer flushes with offsets
+- zink: store and reuse memory heap flags for buffer placement
+- zink: move BAR allocation demotion up the stack
+- zink: be a little selective about BAR fallback memory type
+- zink: add a function for getting the minimum framebuffer layers
+- zink: clamp renderpass layers better
+- zink: move draw-time barrier generation down a little
+- zink: track vertex buffer bind counts on resources
+- zink: rework buffer barrier generation
+- zink: track image binds
+- zink: add a #define for vk shader bits
+- zink: collect gfx stages for all bindings during barrier generation
+- zink: don't short-circuit gfx stage finding during barrier generation
+- zink: relax zink_resource_buffer_needs_barrier checks
+- zink: cap driver inlining using ssa allocation limit
+- glx/drisw: store the flush extension to the screen
+- glx/drisw: invalidate drawables upon binding context if flush extension exists
+- zink: fix dual_src_blend driconf workaround
+- nir/lower_point_size: apply point size clamping
+- lavapipe: copy more pNexts for pipeline creation
+- lavapipe: fix renderpass info handling during pipeline creation
+- lavapipe: skip post-copy pNext checking during pipeline creation for composites
+- zink: fix image bind counting
+- zink: fix kopper_acquire return value
+
+Renato Pereyra (2):
+
+- Revert "wsi/x11: Don't leak xcb_get_geometry_reply_t."
+- Revert "wsi/x11: Avoid using xcb_wait_for_special_event in FIFO modes"
+
+Rhys Perry (1):
+
+- nir/deref: stop assuming coherent accesses of different SSBOs may alias
+
+Samuel Pitoiset (1):
+
+- aco: fix validation of SOP1 instructions without definitions
+
+Sebastian Keller (1):
+
+- egl/wayland: Don't try to access modifiers u_vector as dynarray
+
+Sviatoslav Peleshko (2):
+
+- intel/blorp/gen6: Set BLEND_STATEChange only if emitting the blend state
+- intel/blorp: Dirty depth bounds dynamic state bits after blorp
+
+Timothy Arceri (2):
+
+- util: add dri config option to disable GL_MAP_UNSYNCHRONIZED_BIT
+- util: use force_gl_map_buffer_synchronized workaround with RAGE
+
+Timur Kristóf (1):
+
+- gallium/u_blitter: Fix depth.
+
+Yiwei Zhang (2):
+
+- venus: fix a bug on buffer cache init failure path
+- venus: fix the queue init failure path
diff --git a/docs/relnotes/22.1.4.rst b/docs/relnotes/22.1.4.rst
new file mode 100644
index 00000000000..5837e0cfa28
--- /dev/null
+++ b/docs/relnotes/22.1.4.rst
@@ -0,0 +1,107 @@
+Mesa 22.1.4 Release Notes / 2022-07-15
+======================================
+
+Mesa 22.1.4 is a bug fix release which fixes bugs found since the 22.1.3 release.
+
+Mesa 22.1.4 implements the OpenGL 4.6 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.6. OpenGL
+4.6 is **only** available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+
+Mesa 22.1.4 implements the Vulkan 1.2 API, but the version reported by
+the apiVersion property of the VkPhysicalDeviceProperties struct
+depends on the particular driver being used.
+
+SHA256 checksum
+---------------
+
+::
+
+ 670d8cbe8b72902a45ea2da68a9da4dc4a5d99c5953a926177adbce1b1640b76 mesa-22.1.4.tar.xz
+
+
+
+New features
+------------
+
+- None
+
+
+Bug fixes
+---------
+
+- r300: Segfault in shaders/closed/steam/kerbal-space-program/1017.shader_test
+
+
+Changes
+-------
+
+Alyssa Rosenzweig (2):
+
+- ttn: Set nir->info.separate_shader
+- panfrost: Clear with a quad to avoid flushing
+
+Daniel Schürmann (3):
+
+- nir/opt_shrink_vectors: fix re-using of components for vecN
+- radv/shader_info: fix load_frag_coord and load_sample_pos read masks
+- aco: fix packed 16bit fneg/fsat optimization
+
+Dylan Baker (6):
+
+- docs: add sah256sum for mesa 22.1.3
+- .pick_status.json: Update to c017dfec62e448fea9ad9d16c575086b0de19b3b
+- .pick_status.json: Mark 4480e577a462d43f5c7701d2c1b70c601c626e18 as denominated
+- .pick_status.json: Update to 8ab1e9826db5936ff287bef7b428ebee27ada507
+- .pick_status.json: Update to 9dbfc21ab9ac99ebec56369d1e1ea9d7b615d5f5
+- .pick_status.json: Update to 0feedec9e6b630f930605d9681911fe9e2b705ce
+
+Emma Anholt (1):
+
+- zink: Do the timestamp-to-ns math in a double to have better precision.
+
+Iago Toral Quiroga (2):
+
+- v3dv: fix pool descriptor count for inline uniform buffers
+- nir: fix documentation for uadd_carry and usub_borry opcodes
+
+Jason Ekstrand (4):
+
+- vulkan/wsi: Pass the size to MapMemory in the SW path
+- vulkan/wsi/x11: Don't leak shm_reply if we don't have dri3 or present
+- anv: Inheritance info cannot be NULL
+- anv: Stop compacting surface state tables
+
+Lionel Landwerlin (5):
+
+- anv: disable non uniform indexing of UBOs
+- anv: use the right helper to invalidate memory
+- intel/fs: ray query fix for global address
+- nir/serialize: restore ray query variables
+- isl: add new helper for format component compatibility
+
+Marek Olšák (1):
+
+- radeonsi: fix random PS wave size
+
+Mike Blumenkrantz (5):
+
+- nir/types: fix glsl_matrix_type_is_row_major() assert
+- zink: enforce viewport depth clamping
+- mesa: fix SignalSemaphoreEXT behavior
+- lavapipe: don't overwrite entire VkFormatProperties3 struct
+- lavapipe: don't crash on null xfb buffer pointer
+
+Pavel Ondračka (1):
+
+- r300: Keep rc_rename_regs() from overflowing RC_REGISTER_MAX_INDEX
+
+Rhys Perry (1):
+
+- aco/ra: update register file when updating phi definition
+
+Tatsuyuki Ishi (1):
+
+- radv: Fix vkCmdCopyQueryResults -> vkCmdResetPool hazard.
diff --git a/docs/relnotes/22.1.5.rst b/docs/relnotes/22.1.5.rst
new file mode 100644
index 00000000000..152e6c9fc28
--- /dev/null
+++ b/docs/relnotes/22.1.5.rst
@@ -0,0 +1,159 @@
+Mesa 22.1.5 Release Notes / 2022-08-03
+======================================
+
+Mesa 22.1.5 is a bug fix release which fixes bugs found since the 22.1.4 release.
+
+Mesa 22.1.5 implements the OpenGL 4.6 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.6. OpenGL
+4.6 is **only** available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+
+Mesa 22.1.5 implements the Vulkan 1.2 API, but the version reported by
+the apiVersion property of the VkPhysicalDeviceProperties struct
+depends on the particular driver being used.
+
+SHA256 checksum
+---------------
+
+::
+
+ 6fd60d38efdd25317948c61494b5117e01d42da695278728b1faef9f5f9a47ba mesa-22.1.5.tar.xz
+
+
+
+New features
+------------
+
+- None
+
+
+Bug fixes
+---------
+
+- radv: dynamic vertex input failure
+- anv: KHR-GL46.tessellation_shader.single.xfb_captures_data_from_correct_stage fails on TGL
+- anv: GTF-GL46.gtf32.GL3Tests.packed_pixels.packed_pixels_pbo failure
+- anv: ICL hiz issue
+- Error compiling gallium-nine on i686 using musl libc
+- [anv][regression][bisected][bsw,gen9atom] dEQP-VK.memory.mapping.dedicated_alloc failing on bsw and gen9atom
+
+
+Changes
+-------
+
+Alyssa Rosenzweig (2):
+
+- pan/bi: Require ATEST coverage mask input in R60
+- panfrost: Add decoupled early-ZS helpers
+
+Bas Nieuwenhuizen (1):
+
+- radv: Skip setting empty index buffers to avoid hang
+
+Brian Paul (5):
+
+- util/bitset: add BITSET_SIZE()
+- llvmpipe: add missing tex_info->texture_unit assignment
+- gallivm: increase LP_MAX_TGSI_SHADER_IMAGES from 16 to 32
+- lavapipe: fix logicop, independent blend enable/disable
+- llvmpipe: don't allow texture/resource swizzles on linear path
+
+Chuansheng Liu (1):
+
+- iris,anv: correct the max thread number for DG2+
+
+Daniel Schürmann (2):
+
+- aco: fix assertion in insert_exec_mask
+- radv/rt: fix nir_builder cursor in lower_rt_instructions()
+
+Dave Airlie (5):
+
+- kms/dri: add mutex lock around map/unmap
+- crocus: fail query begin if upload allocation fails.
+- lavapipe: state latest conformance tests passed
+- llvmpipe: fix aniso cube map arrays.
+- crocus: fix leak in query code.
+
+Dylan Baker (2):
+
+- .pick_status.json: Update to 4cfa777e393705b40cebd0a4cd76aa827ce8b194
+- .pick_status.json: Update to 9b844d7c42129925525d613c19622b11aee16298
+
+Erik Faye-Lund (1):
+
+- zink: fix EXT_color_write_enable check
+
+Iago Toral Quiroga (1):
+
+- v3dv: stop tracking push constant buffer references
+
+Icecream95 (2):
+
+- panfrost: Only emit images when they are present
+- panfrost: Don't unbind recently bound streamout targets
+
+Jason Ekstrand (1):
+
+- vulkan/nir: Don't remove dead XFB outputs
+
+Jesse Natalie (1):
+
+- u_atomic: Fix MSVC p_atomic_add_return
+
+Lionel Landwerlin (7):
+
+- intel: protect against empty invalidate ranges
+- anv: track if images can be fast clear with non-zero color
+- anv: deal with isl format swizzles for buffer views
+- spirv: switch to uint64 for rayquery internal type
+- anv: ensure tile flush before streamout writes
+- intel/fs: Set NonPerspectiveBarycentricEnable when the interpolator needs it.
+- anv: fix primitive topology dynamic state emission on gfx7
+
+Mike Blumenkrantz (11):
+
+- lavapipe: support inlined shader spirv for compute
+- zink: allow multiple tex components for depth tg4
+- zink: always use 32bit sample ops
+- zink: use right glsl length getter for ntv partial stores
+- zink: handle max_vertices=0 in geometry shader
+- zink: handle null samplerview in get_imageview_for_binding()
+- zink: call bind_last_vertex_stage() when binding vs
+- zink: fix viewport count tracking
+- zink: invoke descriptor_program_deinit for programs on context destroy
+- zink: only flag fbfetch as rp update if fbfetch wasn't already configured
+- zink: avoid crashing when bindless texture updates aren't used
+
+Nanley Chery (2):
+
+- iris: Don't leak surface states for compressed resources
+- iris: Don't leak compressed resources in iris_create_surface
+
+Pierre-Eric Pelloux-Prayer (1):
+
+- radeonsi: check last_dirty_buf_counter and dirty_tex_counter
+
+Qiang Yu (2):
+
+- ac/nir/ngg: fix nogs culling scratch size
+- ac/nir/ngg: add a barrier before prim id export
+
+Rhys Perry (1):
+
+- radv: fix vbo_bound_mask indexing
+
+SoroushIMG (2):
+
+- zink: Fix spirv stream 0 vertex emit for multistream shaders
+- Zink: Fix clear being missed when using emulated draws in zink_blit
+
+Timur Kristóf (1):
+
+- ac/llvm: Add LLVM bug workaround to ac_build_mbcnt_add.
+
+newbluemoon (1):
+
+- nine: replace ulimit with sysconf call
diff --git a/docs/relnotes/22.1.6.rst b/docs/relnotes/22.1.6.rst
new file mode 100644
index 00000000000..e69de29bb2d
--- /dev/null
+++ b/docs/relnotes/22.1.6.rst
diff --git a/src/amd/common/ac_nir_lower_ngg.c b/src/amd/common/ac_nir_lower_ngg.c
index 96a14cc1bb9..4e921ec5a70 100644
--- a/src/amd/common/ac_nir_lower_ngg.c
+++ b/src/amd/common/ac_nir_lower_ngg.c
@@ -53,6 +53,7 @@ typedef struct
bool export_prim_id;
bool early_prim_export;
bool use_edgeflags;
+ bool can_cull;
unsigned wave_size;
unsigned max_num_waves;
unsigned num_vertices_per_primitives;
@@ -374,6 +375,17 @@ emit_ngg_nogs_prim_exp_arg(nir_builder *b, lower_ngg_nogs_state *st)
static void
emit_ngg_nogs_prim_export(nir_builder *b, lower_ngg_nogs_state *st, nir_ssa_def *arg)
{
+ bool need_prim_id_store_shared =
+ st->export_prim_id && b->shader->info.stage == MESA_SHADER_VERTEX;
+
+ /* Add barrier if LDS is already used by culling and we need LDS for prim id here. */
+ if (st->can_cull && need_prim_id_store_shared) {
+ nir_scoped_barrier(b, .execution_scope = NIR_SCOPE_WORKGROUP,
+ .memory_scope = NIR_SCOPE_WORKGROUP,
+ .memory_semantics = NIR_MEMORY_ACQ_REL,
+ .memory_modes = nir_var_mem_shared);
+ }
+
nir_ssa_def *gs_thread = st->gs_accepted_var
? nir_load_var(b, st->gs_accepted_var)
: nir_has_input_primitive_amd(b);
@@ -383,7 +395,7 @@ emit_ngg_nogs_prim_export(nir_builder *b, lower_ngg_nogs_state *st, nir_ssa_def
if (!arg)
arg = emit_ngg_nogs_prim_exp_arg(b, st);
- if (st->export_prim_id && b->shader->info.stage == MESA_SHADER_VERTEX) {
+ if (need_prim_id_store_shared) {
nir_ssa_def *prim_valid = nir_ieq_imm(b, nir_ushr_imm(b, arg, 31), 0);
nir_if *if_prim_valid = nir_push_if(b, prim_valid);
{
@@ -1064,7 +1076,7 @@ add_deferred_attribute_culling(nir_builder *b, nir_cf_list *original_extracted_c
unsigned total_es_lds_bytes = pervertex_lds_bytes * nogs_state->max_es_num_vertices;
unsigned max_num_waves = nogs_state->max_num_waves;
unsigned ngg_scratch_lds_base_addr = ALIGN(total_es_lds_bytes, 8u);
- unsigned ngg_scratch_lds_bytes = DIV_ROUND_UP(max_num_waves, 4u);
+ unsigned ngg_scratch_lds_bytes = ALIGN(max_num_waves, 4u);
nogs_state->total_lds_bytes = ngg_scratch_lds_base_addr + ngg_scratch_lds_bytes;
nir_function_impl *impl = nir_shader_get_entrypoint(b->shader);
@@ -1322,6 +1334,7 @@ ac_nir_lower_ngg_nogs(nir_shader *shader,
.export_prim_id = export_prim_id,
.early_prim_export = early_prim_export,
.use_edgeflags = use_edgeflags,
+ .can_cull = can_cull,
.num_vertices_per_primitives = num_vertices_per_primitives,
.provoking_vtx_idx = provoking_vtx_last ? (num_vertices_per_primitives - 1) : 0,
.position_value_var = position_value_var,
diff --git a/src/amd/compiler/aco_insert_exec_mask.cpp b/src/amd/compiler/aco_insert_exec_mask.cpp
index e1dd3929910..b216ec79176 100644
--- a/src/amd/compiler/aco_insert_exec_mask.cpp
+++ b/src/amd/compiler/aco_insert_exec_mask.cpp
@@ -585,7 +585,8 @@ process_instructions(exec_ctx& ctx, Block* block, std::vector<aco_ptr<Instructio
}
} else if (instr->opcode == aco_opcode::p_demote_to_helper) {
/* turn demote into discard_if with only exact masks */
- assert(ctx.info[block->index].exec[0].second == (mask_type_exact | mask_type_global));
+ assert((ctx.info[block->index].exec[0].second & mask_type_exact) &&
+ (ctx.info[block->index].exec[0].second & mask_type_global));
int num;
Temp cond, exit_cond;
diff --git a/src/amd/compiler/aco_optimizer.cpp b/src/amd/compiler/aco_optimizer.cpp
index e2f540c94e3..76f8fc8aac1 100644
--- a/src/amd/compiler/aco_optimizer.cpp
+++ b/src/amd/compiler/aco_optimizer.cpp
@@ -3326,7 +3326,8 @@ combine_vop3p(opt_ctx& ctx, aco_ptr<Instruction>& instr)
/* apply clamp */
if (instr->opcode == aco_opcode::v_pk_mul_f16 && instr->operands[1].constantEquals(0x3C00) &&
- vop3p->clamp && instr->operands[0].isTemp() && ctx.uses[instr->operands[0].tempId()] == 1) {
+ vop3p->clamp && instr->operands[0].isTemp() && ctx.uses[instr->operands[0].tempId()] == 1 &&
+ !((vop3p->opsel_lo | vop3p->opsel_hi) & 2)) {
ssa_info& info = ctx.info[instr->operands[0].tempId()];
if (info.is_vop3p() && instr_info.can_use_output_modifiers[(int)info.instr->opcode]) {
@@ -3350,6 +3351,12 @@ combine_vop3p(opt_ctx& ctx, aco_ptr<Instruction>& instr)
ssa_info& info = ctx.info[op.tempId()];
if (info.is_vop3p() && info.instr->opcode == aco_opcode::v_pk_mul_f16 &&
info.instr->operands[1].constantEquals(0x3C00)) {
+
+ VOP3P_instruction* fneg = &info.instr->vop3p();
+
+ if ((fneg->opsel_lo | fneg->opsel_hi) & 2)
+ continue;
+
Operand ops[3];
for (unsigned j = 0; j < instr->operands.size(); j++)
ops[j] = instr->operands[j];
@@ -3357,7 +3364,6 @@ combine_vop3p(opt_ctx& ctx, aco_ptr<Instruction>& instr)
if (!check_vop3_operands(ctx, instr->operands.size(), ops))
continue;
- VOP3P_instruction* fneg = &info.instr->vop3p();
if (fneg->clamp)
continue;
instr->operands[i] = fneg->operands[0];
diff --git a/src/amd/compiler/aco_register_allocation.cpp b/src/amd/compiler/aco_register_allocation.cpp
index 1f1b52e1e22..589f28144d7 100644
--- a/src/amd/compiler/aco_register_allocation.cpp
+++ b/src/amd/compiler/aco_register_allocation.cpp
@@ -2012,6 +2012,7 @@ get_reg_phi(ra_ctx& ctx, IDSet& live_in, RegisterFile& register_file,
if (prev_phi) {
/* if so, just update that phi's register */
prev_phi->definitions[0].setFixed(pc.second.physReg());
+ register_file.fill(prev_phi->definitions[0]);
ctx.assignments[prev_phi->definitions[0].tempId()] = {pc.second.physReg(),
pc.second.regClass()};
continue;
diff --git a/src/amd/compiler/aco_validate.cpp b/src/amd/compiler/aco_validate.cpp
index 6f76b42995d..4d0dcb66ac4 100644
--- a/src/amd/compiler/aco_validate.cpp
+++ b/src/amd/compiler/aco_validate.cpp
@@ -378,8 +378,9 @@ validate_ir(Program* program)
}
if (instr->isSOP1() || instr->isSOP2()) {
- check(instr->definitions[0].getTemp().type() == RegType::sgpr,
- "Wrong Definition type for SALU instruction", instr.get());
+ if (!instr->definitions.empty())
+ check(instr->definitions[0].getTemp().type() == RegType::sgpr,
+ "Wrong Definition type for SALU instruction", instr.get());
for (const Operand& op : instr->operands) {
check(op.isConstant() || op.regClass().type() <= RegType::sgpr,
"Wrong Operand type for SALU instruction", instr.get());
diff --git a/src/amd/llvm/ac_llvm_build.c b/src/amd/llvm/ac_llvm_build.c
index e10a546d98b..e4ed7a72357 100644
--- a/src/amd/llvm/ac_llvm_build.c
+++ b/src/amd/llvm/ac_llvm_build.c
@@ -3457,21 +3457,28 @@ LLVMValueRef ac_build_writelane(struct ac_llvm_context *ctx, LLVMValueRef src, L
LLVMValueRef ac_build_mbcnt_add(struct ac_llvm_context *ctx, LLVMValueRef mask, LLVMValueRef add_src)
{
+ LLVMValueRef val;
+
if (ctx->wave_size == 32) {
- LLVMValueRef val = ac_build_intrinsic(ctx, "llvm.amdgcn.mbcnt.lo", ctx->i32,
- (LLVMValueRef[]){mask, add_src}, 2, AC_FUNC_ATTR_READNONE);
- ac_set_range_metadata(ctx, val, 0, ctx->wave_size);
- return val;
+ val = ac_build_intrinsic(ctx, "llvm.amdgcn.mbcnt.lo", ctx->i32,
+ (LLVMValueRef[]){mask, ctx->i32_0}, 2, AC_FUNC_ATTR_READNONE);
+ } else {
+ LLVMValueRef mask_vec = LLVMBuildBitCast(ctx->builder, mask, ctx->v2i32, "");
+ LLVMValueRef mask_lo = LLVMBuildExtractElement(ctx->builder, mask_vec, ctx->i32_0, "");
+ LLVMValueRef mask_hi = LLVMBuildExtractElement(ctx->builder, mask_vec, ctx->i32_1, "");
+ val = ac_build_intrinsic(ctx, "llvm.amdgcn.mbcnt.lo", ctx->i32,
+ (LLVMValueRef[]){mask_lo, ctx->i32_0}, 2, AC_FUNC_ATTR_READNONE);
+ val = ac_build_intrinsic(ctx, "llvm.amdgcn.mbcnt.hi", ctx->i32, (LLVMValueRef[]){mask_hi, val},
+ 2, AC_FUNC_ATTR_READNONE);
}
- LLVMValueRef mask_vec = LLVMBuildBitCast(ctx->builder, mask, ctx->v2i32, "");
- LLVMValueRef mask_lo = LLVMBuildExtractElement(ctx->builder, mask_vec, ctx->i32_0, "");
- LLVMValueRef mask_hi = LLVMBuildExtractElement(ctx->builder, mask_vec, ctx->i32_1, "");
- LLVMValueRef val =
- ac_build_intrinsic(ctx, "llvm.amdgcn.mbcnt.lo", ctx->i32,
- (LLVMValueRef[]){mask_lo, add_src}, 2, AC_FUNC_ATTR_READNONE);
- val = ac_build_intrinsic(ctx, "llvm.amdgcn.mbcnt.hi", ctx->i32, (LLVMValueRef[]){mask_hi, val},
- 2, AC_FUNC_ATTR_READNONE);
- ac_set_range_metadata(ctx, val, 0, ctx->wave_size);
+
+ /* Bug workaround. LLVM always believes the upper bound of mbcnt to be the wave size,
+ * regardless of ac_set_range_metadata. Use an extra add instruction to work around it.
+ */
+ if (add_src != NULL && add_src != ctx->i32_0) {
+ return LLVMBuildAdd(ctx->builder, val, add_src, "");
+ }
+
return val;
}
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index f318f0e50f4..875f196f29c 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2631,12 +2631,15 @@ radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer, bool indirect)
if (!indirect)
return;
- radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
- radeon_emit(cs, state->index_va);
- radeon_emit(cs, state->index_va >> 32);
+ if (state->max_index_count ||
+ !cmd_buffer->device->physical_device->rad_info.has_zero_index_buffer_bug) {
+ radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
+ radeon_emit(cs, state->index_va);
+ radeon_emit(cs, state->index_va >> 32);
- radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
- radeon_emit(cs, state->max_index_count);
+ radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
+ radeon_emit(cs, state->max_index_count);
+ }
cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
}
@@ -5654,11 +5657,11 @@ radv_CmdSetVertexInputEXT(VkCommandBuffer commandBuffer, uint32_t vertexBindingD
unsigned bit = 1u << loc;
if (binding->stride & format_align_req_minus_1) {
state->misaligned_mask |= bit;
- if (cmd_buffer->state.vbo_bound_mask & bit)
+ if (cmd_buffer->state.vbo_bound_mask & BITFIELD_BIT(attrib->binding))
cmd_buffer->state.vbo_misaligned_mask |= bit;
} else {
state->possibly_misaligned_mask |= bit;
- if (cmd_buffer->state.vbo_bound_mask & bit &&
+ if (cmd_buffer->state.vbo_bound_mask & BITFIELD_BIT(attrib->binding) &&
((vb[attrib->binding].offset + state->offsets[loc]) & format_align_req_minus_1))
cmd_buffer->state.vbo_misaligned_mask |= bit;
}
diff --git a/src/amd/vulkan/radv_pipeline_rt.c b/src/amd/vulkan/radv_pipeline_rt.c
index c18e23d0d11..823be535236 100644
--- a/src/amd/vulkan/radv_pipeline_rt.c
+++ b/src/amd/vulkan/radv_pipeline_rt.c
@@ -558,6 +558,7 @@ lower_rt_instructions(nir_shader *shader, struct rt_variables *vars, unsigned ca
}
case nir_intrinsic_load_ray_world_to_object: {
unsigned c = nir_intrinsic_column(intr);
+ b_shader.cursor = nir_instr_remove(instr);
nir_ssa_def *instance_node_addr = nir_load_var(&b_shader, vars->instance_addr);
nir_ssa_def *wto_matrix[3];
nir_build_wto_matrix_load(&b_shader, instance_node_addr, wto_matrix);
@@ -570,12 +571,12 @@ lower_rt_instructions(nir_shader *shader, struct rt_variables *vars, unsigned ca
if (c == 3)
val = nir_fneg(&b_shader,
nir_build_vec3_mat_mult(&b_shader, val, wto_matrix, false));
- b_shader.cursor = nir_instr_remove(instr);
nir_ssa_def_rewrite_uses(&intr->dest.ssa, val);
break;
}
case nir_intrinsic_load_ray_object_to_world: {
unsigned c = nir_intrinsic_column(intr);
+ b_shader.cursor = nir_instr_remove(instr);
nir_ssa_def *instance_node_addr = nir_load_var(&b_shader, vars->instance_addr);
nir_ssa_def *val;
if (c == 3) {
@@ -592,11 +593,11 @@ lower_rt_instructions(nir_shader *shader, struct rt_variables *vars, unsigned ca
nir_iadd(&b_shader, instance_node_addr,
nir_imm_int64(&b_shader, 92 + c * 12)));
}
- b_shader.cursor = nir_instr_remove(instr);
nir_ssa_def_rewrite_uses(&intr->dest.ssa, val);
break;
}
case nir_intrinsic_load_ray_object_origin: {
+ b_shader.cursor = nir_instr_remove(instr);
nir_ssa_def *instance_node_addr = nir_load_var(&b_shader, vars->instance_addr);
nir_ssa_def *wto_matrix[] = {
nir_build_load_global(
@@ -613,17 +614,16 @@ lower_rt_instructions(nir_shader *shader, struct rt_variables *vars, unsigned ca
.align_mul = 64, .align_offset = 48)};
nir_ssa_def *val = nir_build_vec3_mat_mult_pre(
&b_shader, nir_load_var(&b_shader, vars->origin), wto_matrix);
- b_shader.cursor = nir_instr_remove(instr);
nir_ssa_def_rewrite_uses(&intr->dest.ssa, val);
break;
}
case nir_intrinsic_load_ray_object_direction: {
+ b_shader.cursor = nir_instr_remove(instr);
nir_ssa_def *instance_node_addr = nir_load_var(&b_shader, vars->instance_addr);
nir_ssa_def *wto_matrix[3];
nir_build_wto_matrix_load(&b_shader, instance_node_addr, wto_matrix);
nir_ssa_def *val = nir_build_vec3_mat_mult(
&b_shader, nir_load_var(&b_shader, vars->direction), wto_matrix, false);
- b_shader.cursor = nir_instr_remove(instr);
nir_ssa_def_rewrite_uses(&intr->dest.ssa, val);
break;
}
diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index beff321005f..9db3d4ba2be 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -854,6 +854,13 @@ radv_query_shader(struct radv_cmd_buffer *cmd_buffer, VkPipeline *pipeline,
radv_unaligned_dispatch(cmd_buffer, count, 1, 1);
+ /* Ensure that the query copy dispatch is complete before a potential vkCmdResetPool because
+ * there is an implicit execution dependency from each such query command to all query commands
+ * previously submitted to the same queue.
+ */
+ cmd_buffer->active_query_flush_bits |=
+ RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_L2 | RADV_CMD_FLAG_INV_VCACHE;
+
/* Restore conditional rendering. */
cmd_buffer->state.predicating = old_predicating;
diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c
index f374ad29773..efb238fb5df 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -200,10 +200,10 @@ gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
info->ps.reads_front_face = true;
break;
case nir_intrinsic_load_frag_coord:
- info->ps.reads_frag_coord_mask = nir_ssa_def_components_read(&instr->dest.ssa);
+ info->ps.reads_frag_coord_mask |= nir_ssa_def_components_read(&instr->dest.ssa);
break;
case nir_intrinsic_load_sample_pos:
- info->ps.reads_sample_pos_mask = nir_ssa_def_components_read(&instr->dest.ssa);
+ info->ps.reads_sample_pos_mask |= nir_ssa_def_components_read(&instr->dest.ssa);
break;
case nir_intrinsic_load_view_index:
info->uses_view_index = true;
diff --git a/src/broadcom/ci/broadcom-rpi3-fails.txt b/src/broadcom/ci/broadcom-rpi3-fails.txt
index 430b381c44b..c0b04cdb4d4 100644
--- a/src/broadcom/ci/broadcom-rpi3-fails.txt
+++ b/src/broadcom/ci/broadcom-rpi3-fails.txt
@@ -366,31 +366,9 @@ KHR-GLES2.texture_3d.filtering.sizes.63x63x63_nearest_mipmap_linear,Fail
KHR-GLES2.texture_3d.filtering.sizes.63x63x63_nearest_mipmap_nearest,Fail
KHR-GLES2.texture_3d.framebuffer_texture.rgba,Fail
KHR-GLES2.texture_3d.sub_image.rgba8,Fail
-dEQP-EGL.functional.color_clears.multi_context.gles2.rgb888_pbuffer,Crash
-dEQP-EGL.functional.color_clears.multi_context.gles2.rgb888_window,Crash
-dEQP-EGL.functional.color_clears.multi_context.gles2.rgba8888_pbuffer,Crash
-dEQP-EGL.functional.color_clears.multi_context.gles2.rgba8888_window,Crash
-dEQP-EGL.functional.color_clears.multi_thread.gles2.rgb888_pbuffer,Crash
-dEQP-EGL.functional.color_clears.multi_thread.gles2.rgb888_window,Crash
-dEQP-EGL.functional.color_clears.multi_thread.gles2.rgba8888_pbuffer,Crash
-dEQP-EGL.functional.color_clears.multi_thread.gles2.rgba8888_window,Crash
-dEQP-EGL.functional.color_clears.single_context.gles2.rgb888_pbuffer,Crash
-dEQP-EGL.functional.color_clears.single_context.gles2.rgb888_window,Crash
-dEQP-EGL.functional.color_clears.single_context.gles2.rgba8888_pbuffer,Crash
-dEQP-EGL.functional.color_clears.single_context.gles2.rgba8888_window,Crash
+
dEQP-EGL.functional.create_context.no_config,Fail
-dEQP-EGL.functional.render.multi_context.gles2.rgb888_pbuffer,Crash
-dEQP-EGL.functional.render.multi_context.gles2.rgb888_window,Crash
-dEQP-EGL.functional.render.multi_context.gles2.rgba8888_pbuffer,Crash
-dEQP-EGL.functional.render.multi_context.gles2.rgba8888_window,Crash
-dEQP-EGL.functional.render.multi_thread.gles2.rgb888_pbuffer,Crash
-dEQP-EGL.functional.render.multi_thread.gles2.rgb888_window,Crash
-dEQP-EGL.functional.render.multi_thread.gles2.rgba8888_pbuffer,Crash
-dEQP-EGL.functional.render.multi_thread.gles2.rgba8888_window,Crash
-dEQP-EGL.functional.render.single_context.gles2.rgb888_pbuffer,Crash
-dEQP-EGL.functional.render.single_context.gles2.rgb888_window,Crash
-dEQP-EGL.functional.render.single_context.gles2.rgba8888_pbuffer,Crash
-dEQP-EGL.functional.render.single_context.gles2.rgba8888_window,Crash
+
dEQP-GLES2.functional.clipping.line.wide_line_clip_viewport_center,Fail
dEQP-GLES2.functional.clipping.line.wide_line_clip_viewport_corner,Fail
dEQP-GLES2.functional.depth_stencil_clear.depth_stencil_masked,Fail
@@ -412,15 +390,11 @@ dEQP-GLES2.functional.texture.specification.basic_copytexsubimage2d.2d_rgba,Fail
dEQP-GLES2.functional.texture.specification.basic_copytexsubimage2d.cube_rgba,Fail
dEQP-GLES2.functional.texture.wrap.clamp_clamp_nearest_npot_etc1,Fail
-glx@glx-copy-sub-buffer samples=2,Crash
-glx@glx-copy-sub-buffer samples=4,Crash
glx@glx-make-current,Crash
glx@glx-multithread-buffer,Fail
glx@glx-swap