diff options
| -rw-r--r-- | .pick_status.json | 2 | ||||
| -rw-r--r-- | src/amd/common/ac_surface.c | 3 | ||||
| -rw-r--r-- | src/amd/common/ac_surface.h | 3 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_image.c | 25 |
4 files changed, 14 insertions, 19 deletions
diff --git a/.pick_status.json b/.pick_status.json index 8f328791965..67d7c21919c 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -5629,7 +5629,7 @@ "description": "radv: Fix mipmap extent adjustment on GFX9+.", "nominated": true, "nomination_type": 0, - "resolution": 0, + "resolution": 1, "master_sha": null, "because_sha": null }, diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index a2e2ad8a5eb..23cf761a1f8 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -1477,6 +1477,9 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, } } + surf->u.gfx9.base_mip_width = mip_info[0].pitch; + surf->u.gfx9.base_mip_height = mip_info[0].height; + if (in->flags.depth) { assert(in->swizzleMode != ADDR_SW_LINEAR); diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h index e11e5a744de..d7476159f70 100644 --- a/src/amd/common/ac_surface.h +++ b/src/amd/common/ac_surface.h @@ -165,6 +165,9 @@ struct gfx9_surf_layout { /* Mipmap level pitch in elements. Only valid for LINEAR. */ uint16_t pitch[RADEON_SURF_MAX_LEVELS]; + uint16_t base_mip_width; + uint16_t base_mip_height; + uint64_t stencil_offset; /* separate stencil */ /* Displayable DCC. This is always rb_aligned=0 and pipe_aligned=0. diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 440fe4939a8..2a1ba933e42 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -1735,26 +1735,15 @@ radv_image_view_init(struct radv_image_view *iview, * * This means that mip2 will be missing texels. * - * Fix this by calculating the base mip's width and height, then convert that, and round it - * back up to get the level 0 size. - * Clamp the converted size between the original values, and next power of two, which - * means we don't oversize the image. + * Fix it by taking the actual extent addrlib assigned to the base mip level. */ - if (device->physical_device->rad_info.chip_class >= GFX9 && + if (device->physical_device->rad_info.chip_class >= GFX9 && vk_format_is_compressed(image->vk_format) && - !vk_format_is_compressed(iview->vk_format)) { - unsigned lvl_width = radv_minify(image->info.width , range->baseMipLevel); - unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel); - - lvl_width = round_up_u32(lvl_width * view_bw, img_bw); - lvl_height = round_up_u32(lvl_height * view_bh, img_bh); - - lvl_width <<= range->baseMipLevel; - lvl_height <<= range->baseMipLevel; - - iview->extent.width = CLAMP(lvl_width, iview->extent.width, iview->image->planes[0].surface.u.gfx9.surf_pitch); - iview->extent.height = CLAMP(lvl_height, iview->extent.height, iview->image->planes[0].surface.u.gfx9.surf_height); - } + !vk_format_is_compressed(iview->vk_format) && + iview->image->info.levels > 1) { + iview->extent.width = iview->image->planes[0].surface.u.gfx9.base_mip_width; + iview->extent.height = iview->image->planes[0].surface.u.gfx9.base_mip_height; + } } iview->base_layer = range->baseArrayLayer; |