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authorFrancisco Jerez <currojerez@riseup.net>2021-05-25 15:43:01 -0700
committerMarge Bot <eric+marge@anholt.net>2021-06-23 07:34:22 +0000
commit63abc083ce5e03843d72465a76fdb93064bc3eb9 (patch)
treeca0a3580c7549fe12e6b2104de067e9bf2de8605 /src
parent5e7f443de05f7865654b280ffab298172b33b863 (diff)
intel/fs: Teach IR about EOT instruction writing the accumulator implicitly on TGL+.
This is unlikely to have had any negative side effect on the original TGL, but will lead to issues on XeHP+ if the software scoreboard pass isn't able to synchronize the accumulator writes. Fixes: a27542c5ddec8 ("intel/compiler: Clear accumulator register before EOT") Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11433>
Diffstat (limited to 'src')
-rw-r--r--src/intel/compiler/brw_shader.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp
index 4aeff34474b..fdec1d535ac 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -1090,7 +1090,8 @@ backend_instruction::writes_accumulator_implicitly(const struct intel_device_inf
((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
(opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP))) ||
(opcode == FS_OPCODE_LINTERP &&
- (!devinfo->has_pln || devinfo->ver <= 6));
+ (!devinfo->has_pln || devinfo->ver <= 6)) ||
+ (eot && devinfo->ver >= 12); /* See Wa_14010017096. */
}
bool